mips_mcu/
core_timer.rs

1//! Core timer (CPO count and compare registers)
2//!
3//! Functions to access the CP0 registers 9 and 11 using the (privileged)
4//! MIPS instructions `mfc0` and `mtc0`.
5//!
6
7/// Read count register (CP0 register 9, select 0)
8#[inline]
9pub fn read_count() -> u32 {
10    extern "C" {
11        fn mips_read_cp0_count() -> u32;
12    }
13    unsafe { mips_read_cp0_count() }
14}
15
16/// Write count register (CP0 register 9, select 0)
17#[inline]
18pub unsafe fn write_count(count: u32) {
19    extern "C" {
20        fn mips_write_cp0_count(count: u32);
21    }
22    mips_write_cp0_count(count);
23}
24
25/// Read compare register (CP0 register 11, select 0)
26#[inline]
27pub fn read_compare() -> u32 {
28    extern "C" {
29        fn mips_read_cp0_compare() -> u32;
30    }
31    unsafe { mips_read_cp0_compare() }
32}
33
34/// Write compare register (CP0 register 11, select 0)
35#[inline]
36pub unsafe fn write_compare(compare: u32) {
37    extern "C" {
38        fn mips_write_cp0_compare(compare: u32);
39    }
40    mips_write_cp0_compare(compare);
41}
mips_mcu/core_timer.rs

mips_mcu/
core_timer.rs
