minroot_cat/lib.rs
1//! Categorical pipeline abstractions for `MinRoot` VDF hardware.
2//!
3//! Models the `MinRoot` pipeline ring using structures from
4//! [`comp_cat_rs`]:
5//!
6//! - **Pipeline stages** as morphisms in a [`Category`](comp_cat_rs::foundation::category::Category)
7//! - **Ring topology** via a [`Traced`](traced::Traced) monoidal category (feedback loops)
8//! - **N-way interleaving** as a product [`Functor`](comp_cat_rs::foundation::functor::Functor)
9//! - **Exponent scanning** as a catamorphism over [`Stream`](comp_cat_rs::effect::stream::Stream)
10//! - **FPGA/ASIC targeting** via the [`Target`](target::Target) trait
11//!
12//! # Examples
13//!
14//! Build the single-round pipeline path and inspect its structure:
15//!
16//! ```
17//! use minroot_cat::pipeline::{PipelineVertex, single_round_path};
18//!
19//! # fn run() -> Result<(), Box<dyn std::error::Error>> {
20//! let path = single_round_path()?;
21//! assert_eq!(path.source(), PipelineVertex::PreSquare.to_vertex());
22//! assert_eq!(path.target(), PipelineVertex::PostReduce.to_vertex());
23//! assert_eq!(path.len(), 3); // SQR -> MUL -> RED
24//! # Ok(())
25//! # }
26//! # run().unwrap_or(());
27//! ```
28
29pub mod interleave;
30pub mod pipeline;
31pub mod schedule;
32pub mod target;
33pub mod traced;