Module target 

FPGA/ASIC target abstraction.

The MinRoot hardware generates target-agnostic Verilog via hdl-cat. Technology-specific cells (clock gating, multiplier hints) are parameterized by the Target trait, allowing a single design to produce correct output for both FPGA prototyping and ASIC fabrication.

Categorically, this is an adjunction between the specification category (target-independent pipeline) and the implementation category (target-specific hardware). The left adjoint maps abstract pipeline stages to concrete cells; the right adjoint forgets implementation details back to the spec.

Structs

Asic

ASIC target configuration.

Fpga

FPGA target configuration.

Enums

ClockGating

Clock gating approach.

MultiplierStrategy

Multiplier implementation strategy.

Traits

Target

A synthesis target with technology-specific cell selection.