1#[doc = "Register `PLL_SIC_SET` reader"]
2pub type R = crate::R<PllSicSetSpec>;
3#[doc = "Register `PLL_SIC_SET` writer"]
4pub type W = crate::W<PllSicSetSpec>;
5#[doc = "Field `PLL_EN_USB_CLKS` reader - Enables the USB clock from PLL to USB PHY"]
6pub type PllEnUsbClksR = crate::BitReader;
7#[doc = "Field `PLL_EN_USB_CLKS` writer - Enables the USB clock from PLL to USB PHY"]
8pub type PllEnUsbClksW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PLL_POWER` reader - Power up the USB PLL"]
10pub type PllPowerR = crate::BitReader;
11#[doc = "Field `PLL_POWER` writer - Power up the USB PLL"]
12pub type PllPowerW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PLL_ENABLE` reader - Enables the clock output from the USB PLL"]
14pub type PllEnableR = crate::BitReader;
15#[doc = "Field `PLL_ENABLE` writer - Enables the clock output from the USB PLL"]
16pub type PllEnableW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PLL_BYPASS` reader - Bypass the USB PLL."]
18pub type PllBypassR = crate::BitReader;
19#[doc = "Field `PLL_BYPASS` writer - Bypass the USB PLL."]
20pub type PllBypassW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Reference bias power down select.\n\nValue on reset: 0"]
22#[cfg_attr(feature = "defmt", derive(defmt::Format))]
23#[derive(Clone, Copy, Debug, PartialEq, Eq)]
24pub enum RefbiasPwdSel {
25 #[doc = "0: Selects PLL_POWER to control the reference bias"]
26 RefbiasPwdSel0 = 0,
27 #[doc = "1: Selects REFBIAS_PWD to control the reference bias"]
28 RefbiasPwdSel1 = 1,
29}
30impl From<RefbiasPwdSel> for bool {
31 #[inline(always)]
32 fn from(variant: RefbiasPwdSel) -> Self {
33 variant as u8 != 0
34 }
35}
36#[doc = "Field `REFBIAS_PWD_SEL` reader - Reference bias power down select."]
37pub type RefbiasPwdSelR = crate::BitReader<RefbiasPwdSel>;
38impl RefbiasPwdSelR {
39 #[doc = "Get enumerated values variant"]
40 #[inline(always)]
41 pub const fn variant(&self) -> RefbiasPwdSel {
42 match self.bits {
43 false => RefbiasPwdSel::RefbiasPwdSel0,
44 true => RefbiasPwdSel::RefbiasPwdSel1,
45 }
46 }
47 #[doc = "Selects PLL_POWER to control the reference bias"]
48 #[inline(always)]
49 pub fn is_refbias_pwd_sel_0(&self) -> bool {
50 *self == RefbiasPwdSel::RefbiasPwdSel0
51 }
52 #[doc = "Selects REFBIAS_PWD to control the reference bias"]
53 #[inline(always)]
54 pub fn is_refbias_pwd_sel_1(&self) -> bool {
55 *self == RefbiasPwdSel::RefbiasPwdSel1
56 }
57}
58#[doc = "Field `REFBIAS_PWD_SEL` writer - Reference bias power down select."]
59pub type RefbiasPwdSelW<'a, REG> = crate::BitWriter<'a, REG, RefbiasPwdSel>;
60impl<'a, REG> RefbiasPwdSelW<'a, REG>
61where
62 REG: crate::Writable + crate::RegisterSpec,
63{
64 #[doc = "Selects PLL_POWER to control the reference bias"]
65 #[inline(always)]
66 pub fn refbias_pwd_sel_0(self) -> &'a mut crate::W<REG> {
67 self.variant(RefbiasPwdSel::RefbiasPwdSel0)
68 }
69 #[doc = "Selects REFBIAS_PWD to control the reference bias"]
70 #[inline(always)]
71 pub fn refbias_pwd_sel_1(self) -> &'a mut crate::W<REG> {
72 self.variant(RefbiasPwdSel::RefbiasPwdSel1)
73 }
74}
75#[doc = "Field `REFBIAS_PWD` reader - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1."]
76pub type RefbiasPwdR = crate::BitReader;
77#[doc = "Field `REFBIAS_PWD` writer - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1."]
78pub type RefbiasPwdW<'a, REG> = crate::BitWriter<'a, REG>;
79#[doc = "Field `PLL_REG_ENABLE` reader - This field controls the USB PLL regulator, set to enable the regulator"]
80pub type PllRegEnableR = crate::BitReader;
81#[doc = "Field `PLL_REG_ENABLE` writer - This field controls the USB PLL regulator, set to enable the regulator"]
82pub type PllRegEnableW<'a, REG> = crate::BitWriter<'a, REG>;
83#[doc = "This field controls the USB PLL feedback loop divider\n\nValue on reset: 3"]
84#[cfg_attr(feature = "defmt", derive(defmt::Format))]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86#[repr(u8)]
87pub enum PllDivSel {
88 #[doc = "0: Divide by 13"]
89 PllDivSel0 = 0,
90 #[doc = "1: Divide by 15"]
91 PllDivSel1 = 1,
92 #[doc = "2: Divide by 16"]
93 PllDivSel2 = 2,
94 #[doc = "3: Divide by 20"]
95 PllDivSel3 = 3,
96 #[doc = "4: Divide by 22"]
97 PllDivSel4 = 4,
98 #[doc = "5: Divide by 25"]
99 PllDivSel5 = 5,
100 #[doc = "6: Divide by 30"]
101 PllDivSel6 = 6,
102 #[doc = "7: Divide by 240"]
103 PllDivSel7 = 7,
104}
105impl From<PllDivSel> for u8 {
106 #[inline(always)]
107 fn from(variant: PllDivSel) -> Self {
108 variant as _
109 }
110}
111impl crate::FieldSpec for PllDivSel {
112 type Ux = u8;
113}
114impl crate::IsEnum for PllDivSel {}
115#[doc = "Field `PLL_DIV_SEL` reader - This field controls the USB PLL feedback loop divider"]
116pub type PllDivSelR = crate::FieldReader<PllDivSel>;
117impl PllDivSelR {
118 #[doc = "Get enumerated values variant"]
119 #[inline(always)]
120 pub const fn variant(&self) -> PllDivSel {
121 match self.bits {
122 0 => PllDivSel::PllDivSel0,
123 1 => PllDivSel::PllDivSel1,
124 2 => PllDivSel::PllDivSel2,
125 3 => PllDivSel::PllDivSel3,
126 4 => PllDivSel::PllDivSel4,
127 5 => PllDivSel::PllDivSel5,
128 6 => PllDivSel::PllDivSel6,
129 7 => PllDivSel::PllDivSel7,
130 _ => unreachable!(),
131 }
132 }
133 #[doc = "Divide by 13"]
134 #[inline(always)]
135 pub fn is_pll_div_sel_0(&self) -> bool {
136 *self == PllDivSel::PllDivSel0
137 }
138 #[doc = "Divide by 15"]
139 #[inline(always)]
140 pub fn is_pll_div_sel_1(&self) -> bool {
141 *self == PllDivSel::PllDivSel1
142 }
143 #[doc = "Divide by 16"]
144 #[inline(always)]
145 pub fn is_pll_div_sel_2(&self) -> bool {
146 *self == PllDivSel::PllDivSel2
147 }
148 #[doc = "Divide by 20"]
149 #[inline(always)]
150 pub fn is_pll_div_sel_3(&self) -> bool {
151 *self == PllDivSel::PllDivSel3
152 }
153 #[doc = "Divide by 22"]
154 #[inline(always)]
155 pub fn is_pll_div_sel_4(&self) -> bool {
156 *self == PllDivSel::PllDivSel4
157 }
158 #[doc = "Divide by 25"]
159 #[inline(always)]
160 pub fn is_pll_div_sel_5(&self) -> bool {
161 *self == PllDivSel::PllDivSel5
162 }
163 #[doc = "Divide by 30"]
164 #[inline(always)]
165 pub fn is_pll_div_sel_6(&self) -> bool {
166 *self == PllDivSel::PllDivSel6
167 }
168 #[doc = "Divide by 240"]
169 #[inline(always)]
170 pub fn is_pll_div_sel_7(&self) -> bool {
171 *self == PllDivSel::PllDivSel7
172 }
173}
174#[doc = "Field `PLL_DIV_SEL` writer - This field controls the USB PLL feedback loop divider"]
175pub type PllDivSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, PllDivSel, crate::Safe>;
176impl<'a, REG> PllDivSelW<'a, REG>
177where
178 REG: crate::Writable + crate::RegisterSpec,
179 REG::Ux: From<u8>,
180{
181 #[doc = "Divide by 13"]
182 #[inline(always)]
183 pub fn pll_div_sel_0(self) -> &'a mut crate::W<REG> {
184 self.variant(PllDivSel::PllDivSel0)
185 }
186 #[doc = "Divide by 15"]
187 #[inline(always)]
188 pub fn pll_div_sel_1(self) -> &'a mut crate::W<REG> {
189 self.variant(PllDivSel::PllDivSel1)
190 }
191 #[doc = "Divide by 16"]
192 #[inline(always)]
193 pub fn pll_div_sel_2(self) -> &'a mut crate::W<REG> {
194 self.variant(PllDivSel::PllDivSel2)
195 }
196 #[doc = "Divide by 20"]
197 #[inline(always)]
198 pub fn pll_div_sel_3(self) -> &'a mut crate::W<REG> {
199 self.variant(PllDivSel::PllDivSel3)
200 }
201 #[doc = "Divide by 22"]
202 #[inline(always)]
203 pub fn pll_div_sel_4(self) -> &'a mut crate::W<REG> {
204 self.variant(PllDivSel::PllDivSel4)
205 }
206 #[doc = "Divide by 25"]
207 #[inline(always)]
208 pub fn pll_div_sel_5(self) -> &'a mut crate::W<REG> {
209 self.variant(PllDivSel::PllDivSel5)
210 }
211 #[doc = "Divide by 30"]
212 #[inline(always)]
213 pub fn pll_div_sel_6(self) -> &'a mut crate::W<REG> {
214 self.variant(PllDivSel::PllDivSel6)
215 }
216 #[doc = "Divide by 240"]
217 #[inline(always)]
218 pub fn pll_div_sel_7(self) -> &'a mut crate::W<REG> {
219 self.variant(PllDivSel::PllDivSel7)
220 }
221}
222#[doc = "USB PLL lock status indicator\n\nValue on reset: 0"]
223#[cfg_attr(feature = "defmt", derive(defmt::Format))]
224#[derive(Clone, Copy, Debug, PartialEq, Eq)]
225pub enum PllLock {
226 #[doc = "0: PLL is not currently locked"]
227 PllLock0 = 0,
228 #[doc = "1: PLL is currently locked"]
229 PllLock1 = 1,
230}
231impl From<PllLock> for bool {
232 #[inline(always)]
233 fn from(variant: PllLock) -> Self {
234 variant as u8 != 0
235 }
236}
237#[doc = "Field `PLL_LOCK` reader - USB PLL lock status indicator"]
238pub type PllLockR = crate::BitReader<PllLock>;
239impl PllLockR {
240 #[doc = "Get enumerated values variant"]
241 #[inline(always)]
242 pub const fn variant(&self) -> PllLock {
243 match self.bits {
244 false => PllLock::PllLock0,
245 true => PllLock::PllLock1,
246 }
247 }
248 #[doc = "PLL is not currently locked"]
249 #[inline(always)]
250 pub fn is_pll_lock_0(&self) -> bool {
251 *self == PllLock::PllLock0
252 }
253 #[doc = "PLL is currently locked"]
254 #[inline(always)]
255 pub fn is_pll_lock_1(&self) -> bool {
256 *self == PllLock::PllLock1
257 }
258}
259#[doc = "Field `PLL_LOCK` writer - USB PLL lock status indicator"]
260pub type PllLockW<'a, REG> = crate::BitWriter<'a, REG, PllLock>;
261impl<'a, REG> PllLockW<'a, REG>
262where
263 REG: crate::Writable + crate::RegisterSpec,
264{
265 #[doc = "PLL is not currently locked"]
266 #[inline(always)]
267 pub fn pll_lock_0(self) -> &'a mut crate::W<REG> {
268 self.variant(PllLock::PllLock0)
269 }
270 #[doc = "PLL is currently locked"]
271 #[inline(always)]
272 pub fn pll_lock_1(self) -> &'a mut crate::W<REG> {
273 self.variant(PllLock::PllLock1)
274 }
275}
276impl R {
277 #[doc = "Bit 6 - Enables the USB clock from PLL to USB PHY"]
278 #[inline(always)]
279 pub fn pll_en_usb_clks(&self) -> PllEnUsbClksR {
280 PllEnUsbClksR::new(((self.bits >> 6) & 1) != 0)
281 }
282 #[doc = "Bit 12 - Power up the USB PLL"]
283 #[inline(always)]
284 pub fn pll_power(&self) -> PllPowerR {
285 PllPowerR::new(((self.bits >> 12) & 1) != 0)
286 }
287 #[doc = "Bit 13 - Enables the clock output from the USB PLL"]
288 #[inline(always)]
289 pub fn pll_enable(&self) -> PllEnableR {
290 PllEnableR::new(((self.bits >> 13) & 1) != 0)
291 }
292 #[doc = "Bit 16 - Bypass the USB PLL."]
293 #[inline(always)]
294 pub fn pll_bypass(&self) -> PllBypassR {
295 PllBypassR::new(((self.bits >> 16) & 1) != 0)
296 }
297 #[doc = "Bit 19 - Reference bias power down select."]
298 #[inline(always)]
299 pub fn refbias_pwd_sel(&self) -> RefbiasPwdSelR {
300 RefbiasPwdSelR::new(((self.bits >> 19) & 1) != 0)
301 }
302 #[doc = "Bit 20 - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1."]
303 #[inline(always)]
304 pub fn refbias_pwd(&self) -> RefbiasPwdR {
305 RefbiasPwdR::new(((self.bits >> 20) & 1) != 0)
306 }
307 #[doc = "Bit 21 - This field controls the USB PLL regulator, set to enable the regulator"]
308 #[inline(always)]
309 pub fn pll_reg_enable(&self) -> PllRegEnableR {
310 PllRegEnableR::new(((self.bits >> 21) & 1) != 0)
311 }
312 #[doc = "Bits 22:24 - This field controls the USB PLL feedback loop divider"]
313 #[inline(always)]
314 pub fn pll_div_sel(&self) -> PllDivSelR {
315 PllDivSelR::new(((self.bits >> 22) & 7) as u8)
316 }
317 #[doc = "Bit 31 - USB PLL lock status indicator"]
318 #[inline(always)]
319 pub fn pll_lock(&self) -> PllLockR {
320 PllLockR::new(((self.bits >> 31) & 1) != 0)
321 }
322}
323#[cfg(feature = "debug")]
324impl core::fmt::Debug for R {
325 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
326 f.debug_struct("PLL_SIC_SET")
327 .field("pll_en_usb_clks", &self.pll_en_usb_clks())
328 .field("pll_power", &self.pll_power())
329 .field("pll_enable", &self.pll_enable())
330 .field("pll_bypass", &self.pll_bypass())
331 .field("refbias_pwd_sel", &self.refbias_pwd_sel())
332 .field("refbias_pwd", &self.refbias_pwd())
333 .field("pll_reg_enable", &self.pll_reg_enable())
334 .field("pll_div_sel", &self.pll_div_sel())
335 .field("pll_lock", &self.pll_lock())
336 .finish()
337 }
338}
339impl W {
340 #[doc = "Bit 6 - Enables the USB clock from PLL to USB PHY"]
341 #[inline(always)]
342 pub fn pll_en_usb_clks(&mut self) -> PllEnUsbClksW<PllSicSetSpec> {
343 PllEnUsbClksW::new(self, 6)
344 }
345 #[doc = "Bit 12 - Power up the USB PLL"]
346 #[inline(always)]
347 pub fn pll_power(&mut self) -> PllPowerW<PllSicSetSpec> {
348 PllPowerW::new(self, 12)
349 }
350 #[doc = "Bit 13 - Enables the clock output from the USB PLL"]
351 #[inline(always)]
352 pub fn pll_enable(&mut self) -> PllEnableW<PllSicSetSpec> {
353 PllEnableW::new(self, 13)
354 }
355 #[doc = "Bit 16 - Bypass the USB PLL."]
356 #[inline(always)]
357 pub fn pll_bypass(&mut self) -> PllBypassW<PllSicSetSpec> {
358 PllBypassW::new(self, 16)
359 }
360 #[doc = "Bit 19 - Reference bias power down select."]
361 #[inline(always)]
362 pub fn refbias_pwd_sel(&mut self) -> RefbiasPwdSelW<PllSicSetSpec> {
363 RefbiasPwdSelW::new(self, 19)
364 }
365 #[doc = "Bit 20 - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1."]
366 #[inline(always)]
367 pub fn refbias_pwd(&mut self) -> RefbiasPwdW<PllSicSetSpec> {
368 RefbiasPwdW::new(self, 20)
369 }
370 #[doc = "Bit 21 - This field controls the USB PLL regulator, set to enable the regulator"]
371 #[inline(always)]
372 pub fn pll_reg_enable(&mut self) -> PllRegEnableW<PllSicSetSpec> {
373 PllRegEnableW::new(self, 21)
374 }
375 #[doc = "Bits 22:24 - This field controls the USB PLL feedback loop divider"]
376 #[inline(always)]
377 pub fn pll_div_sel(&mut self) -> PllDivSelW<PllSicSetSpec> {
378 PllDivSelW::new(self, 22)
379 }
380 #[doc = "Bit 31 - USB PLL lock status indicator"]
381 #[inline(always)]
382 pub fn pll_lock(&mut self) -> PllLockW<PllSicSetSpec> {
383 PllLockW::new(self, 31)
384 }
385}
386#[doc = "USB PHY PLL Control/Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pll_sic_set::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pll_sic_set::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
387pub struct PllSicSetSpec;
388impl crate::RegisterSpec for PllSicSetSpec {
389 type Ux = u32;
390}
391#[doc = "`read()` method returns [`pll_sic_set::R`](R) reader structure"]
392impl crate::Readable for PllSicSetSpec {}
393#[doc = "`write(|w| ..)` method takes [`pll_sic_set::W`](W) writer structure"]
394impl crate::Writable for PllSicSetSpec {
395 type Safety = crate::Unsafe;
396 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
397 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
398}
399#[doc = "`reset()` method sets PLL_SIC_SET to value 0x00d1_2000"]
400impl crate::Resettable for PllSicSetSpec {
401 const RESET_VALUE: u32 = 0x00d1_2000;
402}