1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Field `ENHOSTDISCONDETECT` reader - For host mode, enables high-speed disconnect detector"]
6pub type EnhostdiscondetectR = crate::BitReader;
7#[doc = "Field `ENHOSTDISCONDETECT` writer - For host mode, enables high-speed disconnect detector"]
8pub type EnhostdiscondetectW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `HOSTDISCONDETECT_IRQ` reader - Indicates that the device has disconnected in High-Speed mode"]
10pub type HostdiscondetectIrqR = crate::BitReader;
11#[doc = "Field `HOSTDISCONDETECT_IRQ` writer - Indicates that the device has disconnected in High-Speed mode"]
12pub type HostdiscondetectIrqW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode\n\nValue on reset: 0"]
14#[cfg_attr(feature = "defmt", derive(defmt::Format))]
15#[derive(Clone, Copy, Debug, PartialEq, Eq)]
16pub enum Endevplugindet {
17 #[doc = "0: Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)"]
18 Endevplugindet0 = 0,
19 #[doc = "1: Enables 200kohm pullup resistors on USB_DP and USB_DM pins"]
20 Endevplugindet1 = 1,
21}
22impl From<Endevplugindet> for bool {
23 #[inline(always)]
24 fn from(variant: Endevplugindet) -> Self {
25 variant as u8 != 0
26 }
27}
28#[doc = "Field `ENDEVPLUGINDET` reader - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode"]
29pub type EndevplugindetR = crate::BitReader<Endevplugindet>;
30impl EndevplugindetR {
31 #[doc = "Get enumerated values variant"]
32 #[inline(always)]
33 pub const fn variant(&self) -> Endevplugindet {
34 match self.bits {
35 false => Endevplugindet::Endevplugindet0,
36 true => Endevplugindet::Endevplugindet1,
37 }
38 }
39 #[doc = "Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)"]
40 #[inline(always)]
41 pub fn is_endevplugindet_0(&self) -> bool {
42 *self == Endevplugindet::Endevplugindet0
43 }
44 #[doc = "Enables 200kohm pullup resistors on USB_DP and USB_DM pins"]
45 #[inline(always)]
46 pub fn is_endevplugindet_1(&self) -> bool {
47 *self == Endevplugindet::Endevplugindet1
48 }
49}
50#[doc = "Field `ENDEVPLUGINDET` writer - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode"]
51pub type EndevplugindetW<'a, REG> = crate::BitWriter<'a, REG, Endevplugindet>;
52impl<'a, REG> EndevplugindetW<'a, REG>
53where
54 REG: crate::Writable + crate::RegisterSpec,
55{
56 #[doc = "Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)"]
57 #[inline(always)]
58 pub fn endevplugindet_0(self) -> &'a mut crate::W<REG> {
59 self.variant(Endevplugindet::Endevplugindet0)
60 }
61 #[doc = "Enables 200kohm pullup resistors on USB_DP and USB_DM pins"]
62 #[inline(always)]
63 pub fn endevplugindet_1(self) -> &'a mut crate::W<REG> {
64 self.variant(Endevplugindet::Endevplugindet1)
65 }
66}
67#[doc = "Field `DEVPLUGIN_IRQ` reader - Indicates that the device is connected"]
68pub type DevpluginIrqR = crate::BitReader;
69#[doc = "Field `DEVPLUGIN_IRQ` writer - Indicates that the device is connected"]
70pub type DevpluginIrqW<'a, REG> = crate::BitWriter<'a, REG>;
71#[doc = "Field `ENUTMILEVEL2` reader - Enables UTMI+ Level 2 operation for the USB HS PHY"]
72pub type Enutmilevel2R = crate::BitReader;
73#[doc = "Field `ENUTMILEVEL2` writer - Enables UTMI+ Level 2 operation for the USB HS PHY"]
74pub type Enutmilevel2W<'a, REG> = crate::BitWriter<'a, REG>;
75#[doc = "Field `ENUTMILEVEL3` reader - Enables UTMI+ Level 3 operation for the USB HS PHY"]
76pub type Enutmilevel3R = crate::BitReader;
77#[doc = "Field `ENUTMILEVEL3` writer - Enables UTMI+ Level 3 operation for the USB HS PHY"]
78pub type Enutmilevel3W<'a, REG> = crate::BitWriter<'a, REG>;
79#[doc = "Field `AUTORESUME_EN` reader - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)"]
80pub type AutoresumeEnR = crate::BitReader;
81#[doc = "Field `AUTORESUME_EN` writer - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)"]
82pub type AutoresumeEnW<'a, REG> = crate::BitWriter<'a, REG>;
83#[doc = "Field `ENAUTOCLR_CLKGATE` reader - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended"]
84pub type EnautoclrClkgateR = crate::BitReader;
85#[doc = "Field `ENAUTOCLR_CLKGATE` writer - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended"]
86pub type EnautoclrClkgateW<'a, REG> = crate::BitWriter<'a, REG>;
87#[doc = "Field `ENAUTOCLR_PHY_PWD` reader - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended"]
88pub type EnautoclrPhyPwdR = crate::BitReader;
89#[doc = "Field `ENAUTOCLR_PHY_PWD` writer - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended"]
90pub type EnautoclrPhyPwdW<'a, REG> = crate::BitWriter<'a, REG>;
91#[doc = "Field `FSDLL_RST_EN` reader - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet."]
92pub type FsdllRstEnR = crate::BitReader;
93#[doc = "Field `FSDLL_RST_EN` writer - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet."]
94pub type FsdllRstEnW<'a, REG> = crate::BitWriter<'a, REG>;
95#[doc = "Field `HOST_FORCE_LS_SE0` reader - Forces the next FS packet that is transmitted to have a EOP with low-speed timing"]
96pub type HostForceLsSe0R = crate::BitReader;
97#[doc = "Field `HOST_FORCE_LS_SE0` writer - Forces the next FS packet that is transmitted to have a EOP with low-speed timing"]
98pub type HostForceLsSe0W<'a, REG> = crate::BitWriter<'a, REG>;
99#[doc = "Field `UTMI_SUSPENDM` reader - Used by the PHY to indicate a powered-down state"]
100pub type UtmiSuspendmR = crate::BitReader;
101#[doc = "Field `UTMI_SUSPENDM` writer - Used by the PHY to indicate a powered-down state"]
102pub type UtmiSuspendmW<'a, REG> = crate::BitWriter<'a, REG>;
103#[doc = "Field `CLKGATE` reader - Gate UTMI Clocks"]
104pub type ClkgateR = crate::BitReader;
105#[doc = "Field `CLKGATE` writer - Gate UTMI Clocks"]
106pub type ClkgateW<'a, REG> = crate::BitWriter<'a, REG>;
107#[doc = "Field `SFTRST` reader - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers"]
108pub type SftrstR = crate::BitReader;
109#[doc = "Field `SFTRST` writer - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers"]
110pub type SftrstW<'a, REG> = crate::BitWriter<'a, REG>;
111impl R {
112 #[doc = "Bit 1 - For host mode, enables high-speed disconnect detector"]
113 #[inline(always)]
114 pub fn enhostdiscondetect(&self) -> EnhostdiscondetectR {
115 EnhostdiscondetectR::new(((self.bits >> 1) & 1) != 0)
116 }
117 #[doc = "Bit 3 - Indicates that the device has disconnected in High-Speed mode"]
118 #[inline(always)]
119 pub fn hostdiscondetect_irq(&self) -> HostdiscondetectIrqR {
120 HostdiscondetectIrqR::new(((self.bits >> 3) & 1) != 0)
121 }
122 #[doc = "Bit 4 - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode"]
123 #[inline(always)]
124 pub fn endevplugindet(&self) -> EndevplugindetR {
125 EndevplugindetR::new(((self.bits >> 4) & 1) != 0)
126 }
127 #[doc = "Bit 12 - Indicates that the device is connected"]
128 #[inline(always)]
129 pub fn devplugin_irq(&self) -> DevpluginIrqR {
130 DevpluginIrqR::new(((self.bits >> 12) & 1) != 0)
131 }
132 #[doc = "Bit 14 - Enables UTMI+ Level 2 operation for the USB HS PHY"]
133 #[inline(always)]
134 pub fn enutmilevel2(&self) -> Enutmilevel2R {
135 Enutmilevel2R::new(((self.bits >> 14) & 1) != 0)
136 }
137 #[doc = "Bit 15 - Enables UTMI+ Level 3 operation for the USB HS PHY"]
138 #[inline(always)]
139 pub fn enutmilevel3(&self) -> Enutmilevel3R {
140 Enutmilevel3R::new(((self.bits >> 15) & 1) != 0)
141 }
142 #[doc = "Bit 18 - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)"]
143 #[inline(always)]
144 pub fn autoresume_en(&self) -> AutoresumeEnR {
145 AutoresumeEnR::new(((self.bits >> 18) & 1) != 0)
146 }
147 #[doc = "Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended"]
148 #[inline(always)]
149 pub fn enautoclr_clkgate(&self) -> EnautoclrClkgateR {
150 EnautoclrClkgateR::new(((self.bits >> 19) & 1) != 0)
151 }
152 #[doc = "Bit 20 - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended"]
153 #[inline(always)]
154 pub fn enautoclr_phy_pwd(&self) -> EnautoclrPhyPwdR {
155 EnautoclrPhyPwdR::new(((self.bits >> 20) & 1) != 0)
156 }
157 #[doc = "Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet."]
158 #[inline(always)]
159 pub fn fsdll_rst_en(&self) -> FsdllRstEnR {
160 FsdllRstEnR::new(((self.bits >> 24) & 1) != 0)
161 }
162 #[doc = "Bit 28 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing"]
163 #[inline(always)]
164 pub fn host_force_ls_se0(&self) -> HostForceLsSe0R {
165 HostForceLsSe0R::new(((self.bits >> 28) & 1) != 0)
166 }
167 #[doc = "Bit 29 - Used by the PHY to indicate a powered-down state"]
168 #[inline(always)]
169 pub fn utmi_suspendm(&self) -> UtmiSuspendmR {
170 UtmiSuspendmR::new(((self.bits >> 29) & 1) != 0)
171 }
172 #[doc = "Bit 30 - Gate UTMI Clocks"]
173 #[inline(always)]
174 pub fn clkgate(&self) -> ClkgateR {
175 ClkgateR::new(((self.bits >> 30) & 1) != 0)
176 }
177 #[doc = "Bit 31 - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers"]
178 #[inline(always)]
179 pub fn sftrst(&self) -> SftrstR {
180 SftrstR::new(((self.bits >> 31) & 1) != 0)
181 }
182}
183#[cfg(feature = "debug")]
184impl core::fmt::Debug for R {
185 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
186 f.debug_struct("CTRL")
187 .field("enhostdiscondetect", &self.enhostdiscondetect())
188 .field("hostdiscondetect_irq", &self.hostdiscondetect_irq())
189 .field("endevplugindet", &self.endevplugindet())
190 .field("devplugin_irq", &self.devplugin_irq())
191 .field("enutmilevel2", &self.enutmilevel2())
192 .field("enutmilevel3", &self.enutmilevel3())
193 .field("autoresume_en", &self.autoresume_en())
194 .field("enautoclr_clkgate", &self.enautoclr_clkgate())
195 .field("enautoclr_phy_pwd", &self.enautoclr_phy_pwd())
196 .field("fsdll_rst_en", &self.fsdll_rst_en())
197 .field("host_force_ls_se0", &self.host_force_ls_se0())
198 .field("utmi_suspendm", &self.utmi_suspendm())
199 .field("clkgate", &self.clkgate())
200 .field("sftrst", &self.sftrst())
201 .finish()
202 }
203}
204impl W {
205 #[doc = "Bit 1 - For host mode, enables high-speed disconnect detector"]
206 #[inline(always)]
207 pub fn enhostdiscondetect(&mut self) -> EnhostdiscondetectW<CtrlSpec> {
208 EnhostdiscondetectW::new(self, 1)
209 }
210 #[doc = "Bit 3 - Indicates that the device has disconnected in High-Speed mode"]
211 #[inline(always)]
212 pub fn hostdiscondetect_irq(&mut self) -> HostdiscondetectIrqW<CtrlSpec> {
213 HostdiscondetectIrqW::new(self, 3)
214 }
215 #[doc = "Bit 4 - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode"]
216 #[inline(always)]
217 pub fn endevplugindet(&mut self) -> EndevplugindetW<CtrlSpec> {
218 EndevplugindetW::new(self, 4)
219 }
220 #[doc = "Bit 12 - Indicates that the device is connected"]
221 #[inline(always)]
222 pub fn devplugin_irq(&mut self) -> DevpluginIrqW<CtrlSpec> {
223 DevpluginIrqW::new(self, 12)
224 }
225 #[doc = "Bit 14 - Enables UTMI+ Level 2 operation for the USB HS PHY"]
226 #[inline(always)]
227 pub fn enutmilevel2(&mut self) -> Enutmilevel2W<CtrlSpec> {
228 Enutmilevel2W::new(self, 14)
229 }
230 #[doc = "Bit 15 - Enables UTMI+ Level 3 operation for the USB HS PHY"]
231 #[inline(always)]
232 pub fn enutmilevel3(&mut self) -> Enutmilevel3W<CtrlSpec> {
233 Enutmilevel3W::new(self, 15)
234 }
235 #[doc = "Bit 18 - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)"]
236 #[inline(always)]
237 pub fn autoresume_en(&mut self) -> AutoresumeEnW<CtrlSpec> {
238 AutoresumeEnW::new(self, 18)
239 }
240 #[doc = "Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended"]
241 #[inline(always)]
242 pub fn enautoclr_clkgate(&mut self) -> EnautoclrClkgateW<CtrlSpec> {
243 EnautoclrClkgateW::new(self, 19)
244 }
245 #[doc = "Bit 20 - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended"]
246 #[inline(always)]
247 pub fn enautoclr_phy_pwd(&mut self) -> EnautoclrPhyPwdW<CtrlSpec> {
248 EnautoclrPhyPwdW::new(self, 20)
249 }
250 #[doc = "Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet."]
251 #[inline(always)]
252 pub fn fsdll_rst_en(&mut self) -> FsdllRstEnW<CtrlSpec> {
253 FsdllRstEnW::new(self, 24)
254 }
255 #[doc = "Bit 28 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing"]
256 #[inline(always)]
257 pub fn host_force_ls_se0(&mut self) -> HostForceLsSe0W<CtrlSpec> {
258 HostForceLsSe0W::new(self, 28)
259 }
260 #[doc = "Bit 29 - Used by the PHY to indicate a powered-down state"]
261 #[inline(always)]
262 pub fn utmi_suspendm(&mut self) -> UtmiSuspendmW<CtrlSpec> {
263 UtmiSuspendmW::new(self, 29)
264 }
265 #[doc = "Bit 30 - Gate UTMI Clocks"]
266 #[inline(always)]
267 pub fn clkgate(&mut self) -> ClkgateW<CtrlSpec> {
268 ClkgateW::new(self, 30)
269 }
270 #[doc = "Bit 31 - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers"]
271 #[inline(always)]
272 pub fn sftrst(&mut self) -> SftrstW<CtrlSpec> {
273 SftrstW::new(self, 31)
274 }
275}
276#[doc = "USB PHY General Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
277pub struct CtrlSpec;
278impl crate::RegisterSpec for CtrlSpec {
279 type Ux = u32;
280}
281#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
282impl crate::Readable for CtrlSpec {}
283#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
284impl crate::Writable for CtrlSpec {
285 type Safety = crate::Unsafe;
286 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
287 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
288}
289#[doc = "`reset()` method sets CTRL to value 0xc000_0000"]
290impl crate::Resettable for CtrlSpec {
291 const RESET_VALUE: u32 = 0xc000_0000;
292}