mimxrt685s_pac/sysctl1/
sharedctrlset.rs

1#[doc = "Register `SHAREDCTRLSET%s` reader"]
2pub type R = crate::R<SharedctrlsetSpec>;
3#[doc = "Register `SHAREDCTRLSET%s` writer"]
4pub type W = crate::W<SharedctrlsetSpec>;
5#[doc = "Shared SCK Select. . .\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Sharedscksel {
10    #[doc = "0: FLEXCOMM0"]
11    Flexcomm0 = 0,
12    #[doc = "1: FLEXCOMM1"]
13    Flexcomm1 = 1,
14    #[doc = "2: FLEXCOMM2"]
15    Flexcomm2 = 2,
16    #[doc = "3: FLEXCOMM3"]
17    Flexcomm3 = 3,
18    #[doc = "4: FLEXCOMM4"]
19    Flexcomm4 = 4,
20    #[doc = "5: FLEXCOMM5"]
21    Flexcomm5 = 5,
22    #[doc = "6: FLEXCOMM6"]
23    Flexcomm6 = 6,
24    #[doc = "7: FLEXCOMM7"]
25    Flexcomm7 = 7,
26}
27impl From<Sharedscksel> for u8 {
28    #[inline(always)]
29    fn from(variant: Sharedscksel) -> Self {
30        variant as _
31    }
32}
33impl crate::FieldSpec for Sharedscksel {
34    type Ux = u8;
35}
36impl crate::IsEnum for Sharedscksel {}
37#[doc = "Field `SHAREDSCKSEL` reader - Shared SCK Select. . ."]
38pub type SharedsckselR = crate::FieldReader<Sharedscksel>;
39impl SharedsckselR {
40    #[doc = "Get enumerated values variant"]
41    #[inline(always)]
42    pub const fn variant(&self) -> Sharedscksel {
43        match self.bits {
44            0 => Sharedscksel::Flexcomm0,
45            1 => Sharedscksel::Flexcomm1,
46            2 => Sharedscksel::Flexcomm2,
47            3 => Sharedscksel::Flexcomm3,
48            4 => Sharedscksel::Flexcomm4,
49            5 => Sharedscksel::Flexcomm5,
50            6 => Sharedscksel::Flexcomm6,
51            7 => Sharedscksel::Flexcomm7,
52            _ => unreachable!(),
53        }
54    }
55    #[doc = "FLEXCOMM0"]
56    #[inline(always)]
57    pub fn is_flexcomm0(&self) -> bool {
58        *self == Sharedscksel::Flexcomm0
59    }
60    #[doc = "FLEXCOMM1"]
61    #[inline(always)]
62    pub fn is_flexcomm1(&self) -> bool {
63        *self == Sharedscksel::Flexcomm1
64    }
65    #[doc = "FLEXCOMM2"]
66    #[inline(always)]
67    pub fn is_flexcomm2(&self) -> bool {
68        *self == Sharedscksel::Flexcomm2
69    }
70    #[doc = "FLEXCOMM3"]
71    #[inline(always)]
72    pub fn is_flexcomm3(&self) -> bool {
73        *self == Sharedscksel::Flexcomm3
74    }
75    #[doc = "FLEXCOMM4"]
76    #[inline(always)]
77    pub fn is_flexcomm4(&self) -> bool {
78        *self == Sharedscksel::Flexcomm4
79    }
80    #[doc = "FLEXCOMM5"]
81    #[inline(always)]
82    pub fn is_flexcomm5(&self) -> bool {
83        *self == Sharedscksel::Flexcomm5
84    }
85    #[doc = "FLEXCOMM6"]
86    #[inline(always)]
87    pub fn is_flexcomm6(&self) -> bool {
88        *self == Sharedscksel::Flexcomm6
89    }
90    #[doc = "FLEXCOMM7"]
91    #[inline(always)]
92    pub fn is_flexcomm7(&self) -> bool {
93        *self == Sharedscksel::Flexcomm7
94    }
95}
96#[doc = "Field `SHAREDSCKSEL` writer - Shared SCK Select. . ."]
97pub type SharedsckselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sharedscksel, crate::Safe>;
98impl<'a, REG> SharedsckselW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101    REG::Ux: From<u8>,
102{
103    #[doc = "FLEXCOMM0"]
104    #[inline(always)]
105    pub fn flexcomm0(self) -> &'a mut crate::W<REG> {
106        self.variant(Sharedscksel::Flexcomm0)
107    }
108    #[doc = "FLEXCOMM1"]
109    #[inline(always)]
110    pub fn flexcomm1(self) -> &'a mut crate::W<REG> {
111        self.variant(Sharedscksel::Flexcomm1)
112    }
113    #[doc = "FLEXCOMM2"]
114    #[inline(always)]
115    pub fn flexcomm2(self) -> &'a mut crate::W<REG> {
116        self.variant(Sharedscksel::Flexcomm2)
117    }
118    #[doc = "FLEXCOMM3"]
119    #[inline(always)]
120    pub fn flexcomm3(self) -> &'a mut crate::W<REG> {
121        self.variant(Sharedscksel::Flexcomm3)
122    }
123    #[doc = "FLEXCOMM4"]
124    #[inline(always)]
125    pub fn flexcomm4(self) -> &'a mut crate::W<REG> {
126        self.variant(Sharedscksel::Flexcomm4)
127    }
128    #[doc = "FLEXCOMM5"]
129    #[inline(always)]
130    pub fn flexcomm5(self) -> &'a mut crate::W<REG> {
131        self.variant(Sharedscksel::Flexcomm5)
132    }
133    #[doc = "FLEXCOMM6"]
134    #[inline(always)]
135    pub fn flexcomm6(self) -> &'a mut crate::W<REG> {
136        self.variant(Sharedscksel::Flexcomm6)
137    }
138    #[doc = "FLEXCOMM7"]
139    #[inline(always)]
140    pub fn flexcomm7(self) -> &'a mut crate::W<REG> {
141        self.variant(Sharedscksel::Flexcomm7)
142    }
143}
144#[doc = "Shared WS Select. . .\n\nValue on reset: 0"]
145#[cfg_attr(feature = "defmt", derive(defmt::Format))]
146#[derive(Clone, Copy, Debug, PartialEq, Eq)]
147#[repr(u8)]
148pub enum Sharedwssel {
149    #[doc = "0: FLEXCOMM0"]
150    Flexcomm0 = 0,
151    #[doc = "1: FLEXCOMM1"]
152    Flexcomm1 = 1,
153    #[doc = "2: FLEXCOMM2"]
154    Flexcomm2 = 2,
155    #[doc = "3: FLEXCOMM3"]
156    Flexcomm3 = 3,
157    #[doc = "4: FLEXCOMM4"]
158    Flexcomm4 = 4,
159    #[doc = "5: FLEXCOMM5"]
160    Flexcomm5 = 5,
161    #[doc = "6: FLEXCOMM6"]
162    Flexcomm6 = 6,
163    #[doc = "7: FLEXCOMM7"]
164    Flexcomm7 = 7,
165}
166impl From<Sharedwssel> for u8 {
167    #[inline(always)]
168    fn from(variant: Sharedwssel) -> Self {
169        variant as _
170    }
171}
172impl crate::FieldSpec for Sharedwssel {
173    type Ux = u8;
174}
175impl crate::IsEnum for Sharedwssel {}
176#[doc = "Field `SHAREDWSSEL` reader - Shared WS Select. . ."]
177pub type SharedwsselR = crate::FieldReader<Sharedwssel>;
178impl SharedwsselR {
179    #[doc = "Get enumerated values variant"]
180    #[inline(always)]
181    pub const fn variant(&self) -> Sharedwssel {
182        match self.bits {
183            0 => Sharedwssel::Flexcomm0,
184            1 => Sharedwssel::Flexcomm1,
185            2 => Sharedwssel::Flexcomm2,
186            3 => Sharedwssel::Flexcomm3,
187            4 => Sharedwssel::Flexcomm4,
188            5 => Sharedwssel::Flexcomm5,
189            6 => Sharedwssel::Flexcomm6,
190            7 => Sharedwssel::Flexcomm7,
191            _ => unreachable!(),
192        }
193    }
194    #[doc = "FLEXCOMM0"]
195    #[inline(always)]
196    pub fn is_flexcomm0(&self) -> bool {
197        *self == Sharedwssel::Flexcomm0
198    }
199    #[doc = "FLEXCOMM1"]
200    #[inline(always)]
201    pub fn is_flexcomm1(&self) -> bool {
202        *self == Sharedwssel::Flexcomm1
203    }
204    #[doc = "FLEXCOMM2"]
205    #[inline(always)]
206    pub fn is_flexcomm2(&self) -> bool {
207        *self == Sharedwssel::Flexcomm2
208    }
209    #[doc = "FLEXCOMM3"]
210    #[inline(always)]
211    pub fn is_flexcomm3(&self) -> bool {
212        *self == Sharedwssel::Flexcomm3
213    }
214    #[doc = "FLEXCOMM4"]
215    #[inline(always)]
216    pub fn is_flexcomm4(&self) -> bool {
217        *self == Sharedwssel::Flexcomm4
218    }
219    #[doc = "FLEXCOMM5"]
220    #[inline(always)]
221    pub fn is_flexcomm5(&self) -> bool {
222        *self == Sharedwssel::Flexcomm5
223    }
224    #[doc = "FLEXCOMM6"]
225    #[inline(always)]
226    pub fn is_flexcomm6(&self) -> bool {
227        *self == Sharedwssel::Flexcomm6
228    }
229    #[doc = "FLEXCOMM7"]
230    #[inline(always)]
231    pub fn is_flexcomm7(&self) -> bool {
232        *self == Sharedwssel::Flexcomm7
233    }
234}
235#[doc = "Field `SHAREDWSSEL` writer - Shared WS Select. . ."]
236pub type SharedwsselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sharedwssel, crate::Safe>;
237impl<'a, REG> SharedwsselW<'a, REG>
238where
239    REG: crate::Writable + crate::RegisterSpec,
240    REG::Ux: From<u8>,
241{
242    #[doc = "FLEXCOMM0"]
243    #[inline(always)]
244    pub fn flexcomm0(self) -> &'a mut crate::W<REG> {
245        self.variant(Sharedwssel::Flexcomm0)
246    }
247    #[doc = "FLEXCOMM1"]
248    #[inline(always)]
249    pub fn flexcomm1(self) -> &'a mut crate::W<REG> {
250        self.variant(Sharedwssel::Flexcomm1)
251    }
252    #[doc = "FLEXCOMM2"]
253    #[inline(always)]
254    pub fn flexcomm2(self) -> &'a mut crate::W<REG> {
255        self.variant(Sharedwssel::Flexcomm2)
256    }
257    #[doc = "FLEXCOMM3"]
258    #[inline(always)]
259    pub fn flexcomm3(self) -> &'a mut crate::W<REG> {
260        self.variant(Sharedwssel::Flexcomm3)
261    }
262    #[doc = "FLEXCOMM4"]
263    #[inline(always)]
264    pub fn flexcomm4(self) -> &'a mut crate::W<REG> {
265        self.variant(Sharedwssel::Flexcomm4)
266    }
267    #[doc = "FLEXCOMM5"]
268    #[inline(always)]
269    pub fn flexcomm5(self) -> &'a mut crate::W<REG> {
270        self.variant(Sharedwssel::Flexcomm5)
271    }
272    #[doc = "FLEXCOMM6"]
273    #[inline(always)]
274    pub fn flexcomm6(self) -> &'a mut crate::W<REG> {
275        self.variant(Sharedwssel::Flexcomm6)
276    }
277    #[doc = "FLEXCOMM7"]
278    #[inline(always)]
279    pub fn flexcomm7(self) -> &'a mut crate::W<REG> {
280        self.variant(Sharedwssel::Flexcomm7)
281    }
282}
283#[doc = "Shared DATA Select. . .\n\nValue on reset: 0"]
284#[cfg_attr(feature = "defmt", derive(defmt::Format))]
285#[derive(Clone, Copy, Debug, PartialEq, Eq)]
286#[repr(u8)]
287pub enum Shareddatasel {
288    #[doc = "0: FLEXCOMM0"]
289    Flexcomm0 = 0,
290    #[doc = "1: FLEXCOMM1"]
291    Flexcomm1 = 1,
292    #[doc = "2: FLEXCOMM2"]
293    Flexcomm2 = 2,
294    #[doc = "3: FLEXCOMM3"]
295    Flexcomm3 = 3,
296    #[doc = "4: FLEXCOMM4"]
297    Flexcomm4 = 4,
298    #[doc = "5: FLEXCOMM5"]
299    Flexcomm5 = 5,
300    #[doc = "6: FLEXCOMM6"]
301    Flexcomm6 = 6,
302    #[doc = "7: FLEXCOMM7"]
303    Flexcomm7 = 7,
304}
305impl From<Shareddatasel> for u8 {
306    #[inline(always)]
307    fn from(variant: Shareddatasel) -> Self {
308        variant as _
309    }
310}
311impl crate::FieldSpec for Shareddatasel {
312    type Ux = u8;
313}
314impl crate::IsEnum for Shareddatasel {}
315#[doc = "Field `SHAREDDATASEL` reader - Shared DATA Select. . ."]
316pub type ShareddataselR = crate::FieldReader<Shareddatasel>;
317impl ShareddataselR {
318    #[doc = "Get enumerated values variant"]
319    #[inline(always)]
320    pub const fn variant(&self) -> Shareddatasel {
321        match self.bits {
322            0 => Shareddatasel::Flexcomm0,
323            1 => Shareddatasel::Flexcomm1,
324            2 => Shareddatasel::Flexcomm2,
325            3 => Shareddatasel::Flexcomm3,
326            4 => Shareddatasel::Flexcomm4,
327            5 => Shareddatasel::Flexcomm5,
328            6 => Shareddatasel::Flexcomm6,
329            7 => Shareddatasel::Flexcomm7,
330            _ => unreachable!(),
331        }
332    }
333    #[doc = "FLEXCOMM0"]
334    #[inline(always)]
335    pub fn is_flexcomm0(&self) -> bool {
336        *self == Shareddatasel::Flexcomm0
337    }
338    #[doc = "FLEXCOMM1"]
339    #[inline(always)]
340    pub fn is_flexcomm1(&self) -> bool {
341        *self == Shareddatasel::Flexcomm1
342    }
343    #[doc = "FLEXCOMM2"]
344    #[inline(always)]
345    pub fn is_flexcomm2(&self) -> bool {
346        *self == Shareddatasel::Flexcomm2
347    }
348    #[doc = "FLEXCOMM3"]
349    #[inline(always)]
350    pub fn is_flexcomm3(&self) -> bool {
351        *self == Shareddatasel::Flexcomm3
352    }
353    #[doc = "FLEXCOMM4"]
354    #[inline(always)]
355    pub fn is_flexcomm4(&self) -> bool {
356        *self == Shareddatasel::Flexcomm4
357    }
358    #[doc = "FLEXCOMM5"]
359    #[inline(always)]
360    pub fn is_flexcomm5(&self) -> bool {
361        *self == Shareddatasel::Flexcomm5
362    }
363    #[doc = "FLEXCOMM6"]
364    #[inline(always)]
365    pub fn is_flexcomm6(&self) -> bool {
366        *self == Shareddatasel::Flexcomm6
367    }
368    #[doc = "FLEXCOMM7"]
369    #[inline(always)]
370    pub fn is_flexcomm7(&self) -> bool {
371        *self == Shareddatasel::Flexcomm7
372    }
373}
374#[doc = "Field `SHAREDDATASEL` writer - Shared DATA Select. . ."]
375pub type ShareddataselW<'a, REG> = crate::FieldWriter<'a, REG, 3, Shareddatasel, crate::Safe>;
376impl<'a, REG> ShareddataselW<'a, REG>
377where
378    REG: crate::Writable + crate::RegisterSpec,
379    REG::Ux: From<u8>,
380{
381    #[doc = "FLEXCOMM0"]
382    #[inline(always)]
383    pub fn flexcomm0(self) -> &'a mut crate::W<REG> {
384        self.variant(Shareddatasel::Flexcomm0)
385    }
386    #[doc = "FLEXCOMM1"]
387    #[inline(always)]
388    pub fn flexcomm1(self) -> &'a mut crate::W<REG> {
389        self.variant(Shareddatasel::Flexcomm1)
390    }
391    #[doc = "FLEXCOMM2"]
392    #[inline(always)]
393    pub fn flexcomm2(self) -> &'a mut crate::W<REG> {
394        self.variant(Shareddatasel::Flexcomm2)
395    }
396    #[doc = "FLEXCOMM3"]
397    #[inline(always)]
398    pub fn flexcomm3(self) -> &'a mut crate::W<REG> {
399        self.variant(Shareddatasel::Flexcomm3)
400    }
401    #[doc = "FLEXCOMM4"]
402    #[inline(always)]
403    pub fn flexcomm4(self) -> &'a mut crate::W<REG> {
404        self.variant(Shareddatasel::Flexcomm4)
405    }
406    #[doc = "FLEXCOMM5"]
407    #[inline(always)]
408    pub fn flexcomm5(self) -> &'a mut crate::W<REG> {
409        self.variant(Shareddatasel::Flexcomm5)
410    }
411    #[doc = "FLEXCOMM6"]
412    #[inline(always)]
413    pub fn flexcomm6(self) -> &'a mut crate::W<REG> {
414        self.variant(Shareddatasel::Flexcomm6)
415    }
416    #[doc = "FLEXCOMM7"]
417    #[inline(always)]
418    pub fn flexcomm7(self) -> &'a mut crate::W<REG> {
419        self.variant(Shareddatasel::Flexcomm7)
420    }
421}
422#[doc = "FLEXCOMM0 DATAOUT OUTPUT ENABLE\n\nValue on reset: 0"]
423#[cfg_attr(feature = "defmt", derive(defmt::Format))]
424#[derive(Clone, Copy, Debug, PartialEq, Eq)]
425pub enum Fc0dataouten {
426    #[doc = "0: Input"]
427    Input = 0,
428    #[doc = "1: Output"]
429    Output = 1,
430}
431impl From<Fc0dataouten> for bool {
432    #[inline(always)]
433    fn from(variant: Fc0dataouten) -> Self {
434        variant as u8 != 0
435    }
436}
437#[doc = "Field `FC0DATAOUTEN` reader - FLEXCOMM0 DATAOUT OUTPUT ENABLE"]
438pub type Fc0dataoutenR = crate::BitReader<Fc0dataouten>;
439impl Fc0dataoutenR {
440    #[doc = "Get enumerated values variant"]
441    #[inline(always)]
442    pub const fn variant(&self) -> Fc0dataouten {
443        match self.bits {
444            false => Fc0dataouten::Input,
445            true => Fc0dataouten::Output,
446        }
447    }
448    #[doc = "Input"]
449    #[inline(always)]
450    pub fn is_input(&self) -> bool {
451        *self == Fc0dataouten::Input
452    }
453    #[doc = "Output"]
454    #[inline(always)]
455    pub fn is_output(&self) -> bool {
456        *self == Fc0dataouten::Output
457    }
458}
459#[doc = "Field `FC0DATAOUTEN` writer - FLEXCOMM0 DATAOUT OUTPUT ENABLE"]
460pub type Fc0dataoutenW<'a, REG> = crate::BitWriter<'a, REG, Fc0dataouten>;
461impl<'a, REG> Fc0dataoutenW<'a, REG>
462where
463    REG: crate::Writable + crate::RegisterSpec,
464{
465    #[doc = "Input"]
466    #[inline(always)]
467    pub fn input(self) -> &'a mut crate::W<REG> {
468        self.variant(Fc0dataouten::Input)
469    }
470    #[doc = "Output"]
471    #[inline(always)]
472    pub fn output(self) -> &'a mut crate::W<REG> {
473        self.variant(Fc0dataouten::Output)
474    }
475}
476#[doc = "FLEXCOMM1 DATAOUT OUTPUT ENABLE\n\nValue on reset: 0"]
477#[cfg_attr(feature = "defmt", derive(defmt::Format))]
478#[derive(Clone, Copy, Debug, PartialEq, Eq)]
479pub enum Fc1dataouten {
480    #[doc = "0: Input"]
481    Input = 0,
482    #[doc = "1: Output"]
483    Output = 1,
484}
485impl From<Fc1dataouten> for bool {
486    #[inline(always)]
487    fn from(variant: Fc1dataouten) -> Self {
488        variant as u8 != 0
489    }
490}
491#[doc = "Field `FC1DATAOUTEN` reader - FLEXCOMM1 DATAOUT OUTPUT ENABLE"]
492pub type Fc1dataoutenR = crate::BitReader<Fc1dataouten>;
493impl Fc1dataoutenR {
494    #[doc = "Get enumerated values variant"]
495    #[inline(always)]
496    pub const fn variant(&self) -> Fc1dataouten {
497        match self.bits {
498            false => Fc1dataouten::Input,
499            true => Fc1dataouten::Output,
500        }
501    }
502    #[doc = "Input"]
503    #[inline(always)]
504    pub fn is_input(&self) -> bool {
505        *self == Fc1dataouten::Input
506    }
507    #[doc = "Output"]
508    #[inline(always)]
509    pub fn is_output(&self) -> bool {
510        *self == Fc1dataouten::Output
511    }
512}
513#[doc = "Field `FC1DATAOUTEN` writer - FLEXCOMM1 DATAOUT OUTPUT ENABLE"]
514pub type Fc1dataoutenW<'a, REG> = crate::BitWriter<'a, REG, Fc1dataouten>;
515impl<'a, REG> Fc1dataoutenW<'a, REG>
516where
517    REG: crate::Writable + crate::RegisterSpec,
518{
519    #[doc = "Input"]
520    #[inline(always)]
521    pub fn input(self) -> &'a mut crate::W<REG> {
522        self.variant(Fc1dataouten::Input)
523    }
524    #[doc = "Output"]
525    #[inline(always)]
526    pub fn output(self) -> &'a mut crate::W<REG> {
527        self.variant(Fc1dataouten::Output)
528    }
529}
530#[doc = "FLEXCOMM2 DATAOUT OUTPUT ENABLE\n\nValue on reset: 0"]
531#[cfg_attr(feature = "defmt", derive(defmt::Format))]
532#[derive(Clone, Copy, Debug, PartialEq, Eq)]
533pub enum F20dataouten {
534    #[doc = "0: Input"]
535    Input = 0,
536    #[doc = "1: Output"]
537    Output = 1,
538}
539impl From<F20dataouten> for bool {
540    #[inline(always)]
541    fn from(variant: F20dataouten) -> Self {
542        variant as u8 != 0
543    }
544}
545#[doc = "Field `F20DATAOUTEN` reader - FLEXCOMM2 DATAOUT OUTPUT ENABLE"]
546pub type F20dataoutenR = crate::BitReader<F20dataouten>;
547impl F20dataoutenR {
548    #[doc = "Get enumerated values variant"]
549    #[inline(always)]
550    pub const fn variant(&self) -> F20dataouten {
551        match self.bits {
552            false => F20dataouten::Input,
553            true => F20dataouten::Output,
554        }
555    }
556    #[doc = "Input"]
557    #[inline(always)]
558    pub fn is_input(&self) -> bool {
559        *self == F20dataouten::Input
560    }
561    #[doc = "Output"]
562    #[inline(always)]
563    pub fn is_output(&self) -> bool {
564        *self == F20dataouten::Output
565    }
566}
567#[doc = "Field `F20DATAOUTEN` writer - FLEXCOMM2 DATAOUT OUTPUT ENABLE"]
568pub type F20dataoutenW<'a, REG> = crate::BitWriter<'a, REG, F20dataouten>;
569impl<'a, REG> F20dataoutenW<'a, REG>
570where
571    REG: crate::Writable + crate::RegisterSpec,
572{
573    #[doc = "Input"]
574    #[inline(always)]
575    pub fn input(self) -> &'a mut crate::W<REG> {
576        self.variant(F20dataouten::Input)
577    }
578    #[doc = "Output"]
579    #[inline(always)]
580    pub fn output(self) -> &'a mut crate::W<REG> {
581        self.variant(F20dataouten::Output)
582    }
583}
584#[doc = "FLEXCOMM3 DATAOUT OUTPUT ENABLE\n\nValue on reset: 0"]
585#[cfg_attr(feature = "defmt", derive(defmt::Format))]
586#[derive(Clone, Copy, Debug, PartialEq, Eq)]
587pub enum Fc3dataouten {
588    #[doc = "0: Input"]
589    Input = 0,
590    #[doc = "1: Output"]
591    Output = 1,
592}
593impl From<Fc3dataouten> for bool {
594    #[inline(always)]
595    fn from(variant: Fc3dataouten) -> Self {
596        variant as u8 != 0
597    }
598}
599#[doc = "Field `FC3DATAOUTEN` reader - FLEXCOMM3 DATAOUT OUTPUT ENABLE"]
600pub type Fc3dataoutenR = crate::BitReader<Fc3dataouten>;
601impl Fc3dataoutenR {
602    #[doc = "Get enumerated values variant"]
603    #[inline(always)]
604    pub const fn variant(&self) -> Fc3dataouten {
605        match self.bits {
606            false => Fc3dataouten::Input,
607            true => Fc3dataouten::Output,
608        }
609    }
610    #[doc = "Input"]
611    #[inline(always)]
612    pub fn is_input(&self) -> bool {
613        *self == Fc3dataouten::Input
614    }
615    #[doc = "Output"]
616    #[inline(always)]
617    pub fn is_output(&self) -> bool {
618        *self == Fc3dataouten::Output
619    }
620}
621#[doc = "Field `FC3DATAOUTEN` writer - FLEXCOMM3 DATAOUT OUTPUT ENABLE"]
622pub type Fc3dataoutenW<'a, REG> = crate::BitWriter<'a, REG, Fc3dataouten>;
623impl<'a, REG> Fc3dataoutenW<'a, REG>
624where
625    REG: crate::Writable + crate::RegisterSpec,
626{
627    #[doc = "Input"]
628    #[inline(always)]
629    pub fn input(self) -> &'a mut crate::W<REG> {
630        self.variant(Fc3dataouten::Input)
631    }
632    #[doc = "Output"]
633    #[inline(always)]
634    pub fn output(self) -> &'a mut crate::W<REG> {
635        self.variant(Fc3dataouten::Output)
636    }
637}
638#[doc = "FLEXCOMM4 DATAOUT OUTPUT ENABLE\n\nValue on reset: 0"]
639#[cfg_attr(feature = "defmt", derive(defmt::Format))]
640#[derive(Clone, Copy, Debug, PartialEq, Eq)]
641pub enum Fc4dataouten {
642    #[doc = "0: Input"]
643    Input = 0,
644    #[doc = "1: Output"]
645    Output = 1,
646}
647impl From<Fc4dataouten> for bool {
648    #[inline(always)]
649    fn from(variant: Fc4dataouten) -> Self {
650        variant as u8 != 0
651    }
652}
653#[doc = "Field `FC4DATAOUTEN` reader - FLEXCOMM4 DATAOUT OUTPUT ENABLE"]
654pub type Fc4dataoutenR = crate::BitReader<Fc4dataouten>;
655impl Fc4dataoutenR {
656    #[doc = "Get enumerated values variant"]
657    #[inline(always)]
658    pub const fn variant(&self) -> Fc4dataouten {
659        match self.bits {
660            false => Fc4dataouten::Input,
661            true => Fc4dataouten::Output,
662        }
663    }
664    #[doc = "Input"]
665    #[inline(always)]
666    pub fn is_input(&self) -> bool {
667        *self == Fc4dataouten::Input
668    }
669    #[doc = "Output"]
670    #[inline(always)]
671    pub fn is_output(&self) -> bool {
672        *self == Fc4dataouten::Output
673    }
674}
675#[doc = "Field `FC4DATAOUTEN` writer - FLEXCOMM4 DATAOUT OUTPUT ENABLE"]
676pub type Fc4dataoutenW<'a, REG> = crate::BitWriter<'a, REG, Fc4dataouten>;
677impl<'a, REG> Fc4dataoutenW<'a, REG>
678where
679    REG: crate::Writable + crate::RegisterSpec,
680{
681    #[doc = "Input"]
682    #[inline(always)]
683    pub fn input(self) -> &'a mut crate::W<REG> {
684        self.variant(Fc4dataouten::Input)
685    }
686    #[doc = "Output"]
687    #[inline(always)]
688    pub fn output(self) -> &'a mut crate::W<REG> {
689        self.variant(Fc4dataouten::Output)
690    }
691}
692#[doc = "FLEXCOMM5 DATAOUT OUTPUT ENABLE\n\nValue on reset: 0"]
693#[cfg_attr(feature = "defmt", derive(defmt::Format))]
694#[derive(Clone, Copy, Debug, PartialEq, Eq)]
695pub enum Fc5dataouten {
696    #[doc = "0: Input"]
697    Input = 0,
698    #[doc = "1: Output"]
699    Output = 1,
700}
701impl From<Fc5dataouten> for bool {
702    #[inline(always)]
703    fn from(variant: Fc5dataouten) -> Self {
704        variant as u8 != 0
705    }
706}
707#[doc = "Field `FC5DATAOUTEN` reader - FLEXCOMM5 DATAOUT OUTPUT ENABLE"]
708pub type Fc5dataoutenR = crate::BitReader<Fc5dataouten>;
709impl Fc5dataoutenR {
710    #[doc = "Get enumerated values variant"]
711    #[inline(always)]
712    pub const fn variant(&self) -> Fc5dataouten {
713        match self.bits {
714            false => Fc5dataouten::Input,
715            true => Fc5dataouten::Output,
716        }
717    }
718    #[doc = "Input"]
719    #[inline(always)]
720    pub fn is_input(&self) -> bool {
721        *self == Fc5dataouten::Input
722    }
723    #[doc = "Output"]
724    #[inline(always)]
725    pub fn is_output(&self) -> bool {
726        *self == Fc5dataouten::Output
727    }
728}
729#[doc = "Field `FC5DATAOUTEN` writer - FLEXCOMM5 DATAOUT OUTPUT ENABLE"]
730pub type Fc5dataoutenW<'a, REG> = crate::BitWriter<'a, REG, Fc5dataouten>;
731impl<'a, REG> Fc5dataoutenW<'a, REG>
732where
733    REG: crate::Writable + crate::RegisterSpec,
734{
735    #[doc = "Input"]
736    #[inline(always)]
737    pub fn input(self) -> &'a mut crate::W<REG> {
738        self.variant(Fc5dataouten::Input)
739    }
740    #[doc = "Output"]
741    #[inline(always)]
742    pub fn output(self) -> &'a mut crate::W<REG> {
743        self.variant(Fc5dataouten::Output)
744    }
745}
746#[doc = "FLEXCOMM6 DATAOUT OUTPUT ENABLE\n\nValue on reset: 0"]
747#[cfg_attr(feature = "defmt", derive(defmt::Format))]
748#[derive(Clone, Copy, Debug, PartialEq, Eq)]
749pub enum Fc6dataouten {
750    #[doc = "0: Input"]
751    Input = 0,
752    #[doc = "1: Output"]
753    Output = 1,
754}
755impl From<Fc6dataouten> for bool {
756    #[inline(always)]
757    fn from(variant: Fc6dataouten) -> Self {
758        variant as u8 != 0
759    }
760}
761#[doc = "Field `FC6DATAOUTEN` reader - FLEXCOMM6 DATAOUT OUTPUT ENABLE"]
762pub type Fc6dataoutenR = crate::BitReader<Fc6dataouten>;
763impl Fc6dataoutenR {
764    #[doc = "Get enumerated values variant"]
765    #[inline(always)]
766    pub const fn variant(&self) -> Fc6dataouten {
767        match self.bits {
768            false => Fc6dataouten::Input,
769            true => Fc6dataouten::Output,
770        }
771    }
772    #[doc = "Input"]
773    #[inline(always)]
774    pub fn is_input(&self) -> bool {
775        *self == Fc6dataouten::Input
776    }
777    #[doc = "Output"]
778    #[inline(always)]
779    pub fn is_output(&self) -> bool {
780        *self == Fc6dataouten::Output
781    }
782}
783#[doc = "Field `FC6DATAOUTEN` writer - FLEXCOMM6 DATAOUT OUTPUT ENABLE"]
784pub type Fc6dataoutenW<'a, REG> = crate::BitWriter<'a, REG, Fc6dataouten>;
785impl<'a, REG> Fc6dataoutenW<'a, REG>
786where
787    REG: crate::Writable + crate::RegisterSpec,
788{
789    #[doc = "Input"]
790    #[inline(always)]
791    pub fn input(self) -> &'a mut crate::W<REG> {
792        self.variant(Fc6dataouten::Input)
793    }
794    #[doc = "Output"]
795    #[inline(always)]
796    pub fn output(self) -> &'a mut crate::W<REG> {
797        self.variant(Fc6dataouten::Output)
798    }
799}
800#[doc = "FLEXCOMM7 DATAOUT OUTPUT ENABLE\n\nValue on reset: 0"]
801#[cfg_attr(feature = "defmt", derive(defmt::Format))]
802#[derive(Clone, Copy, Debug, PartialEq, Eq)]
803pub enum Fc7dataouten {
804    #[doc = "0: Input"]
805    Input = 0,
806    #[doc = "1: Output"]
807    Output = 1,
808}
809impl From<Fc7dataouten> for bool {
810    #[inline(always)]
811    fn from(variant: Fc7dataouten) -> Self {
812        variant as u8 != 0
813    }
814}
815#[doc = "Field `FC7DATAOUTEN` reader - FLEXCOMM7 DATAOUT OUTPUT ENABLE"]
816pub type Fc7dataoutenR = crate::BitReader<Fc7dataouten>;
817impl Fc7dataoutenR {
818    #[doc = "Get enumerated values variant"]
819    #[inline(always)]
820    pub const fn variant(&self) -> Fc7dataouten {
821        match self.bits {
822            false => Fc7dataouten::Input,
823            true => Fc7dataouten::Output,
824        }
825    }
826    #[doc = "Input"]
827    #[inline(always)]
828    pub fn is_input(&self) -> bool {
829        *self == Fc7dataouten::Input
830    }
831    #[doc = "Output"]
832    #[inline(always)]
833    pub fn is_output(&self) -> bool {
834        *self == Fc7dataouten::Output
835    }
836}
837#[doc = "Field `FC7DATAOUTEN` writer - FLEXCOMM7 DATAOUT OUTPUT ENABLE"]
838pub type Fc7dataoutenW<'a, REG> = crate::BitWriter<'a, REG, Fc7dataouten>;
839impl<'a, REG> Fc7dataoutenW<'a, REG>
840where
841    REG: crate::Writable + crate::RegisterSpec,
842{
843    #[doc = "Input"]
844    #[inline(always)]
845    pub fn input(self) -> &'a mut crate::W<REG> {
846        self.variant(Fc7dataouten::Input)
847    }
848    #[doc = "Output"]
849    #[inline(always)]
850    pub fn output(self) -> &'a mut crate::W<REG> {
851        self.variant(Fc7dataouten::Output)
852    }
853}
854impl R {
855    #[doc = "Bits 0:2 - Shared SCK Select. . ."]
856    #[inline(always)]
857    pub fn sharedscksel(&self) -> SharedsckselR {
858        SharedsckselR::new((self.bits & 7) as u8)
859    }
860    #[doc = "Bits 4:6 - Shared WS Select. . ."]
861    #[inline(always)]
862    pub fn sharedwssel(&self) -> SharedwsselR {
863        SharedwsselR::new(((self.bits >> 4) & 7) as u8)
864    }
865    #[doc = "Bits 8:10 - Shared DATA Select. . ."]
866    #[inline(always)]
867    pub fn shareddatasel(&self) -> ShareddataselR {
868        ShareddataselR::new(((self.bits >> 8) & 7) as u8)
869    }
870    #[doc = "Bit 16 - FLEXCOMM0 DATAOUT OUTPUT ENABLE"]
871    #[inline(always)]
872    pub fn fc0dataouten(&self) -> Fc0dataoutenR {
873        Fc0dataoutenR::new(((self.bits >> 16) & 1) != 0)
874    }
875    #[doc = "Bit 17 - FLEXCOMM1 DATAOUT OUTPUT ENABLE"]
876    #[inline(always)]
877    pub fn fc1dataouten(&self) -> Fc1dataoutenR {
878        Fc1dataoutenR::new(((self.bits >> 17) & 1) != 0)
879    }
880    #[doc = "Bit 18 - FLEXCOMM2 DATAOUT OUTPUT ENABLE"]
881    #[inline(always)]
882    pub fn f20dataouten(&self) -> F20dataoutenR {
883        F20dataoutenR::new(((self.bits >> 18) & 1) != 0)
884    }
885    #[doc = "Bit 19 - FLEXCOMM3 DATAOUT OUTPUT ENABLE"]
886    #[inline(always)]
887    pub fn fc3dataouten(&self) -> Fc3dataoutenR {
888        Fc3dataoutenR::new(((self.bits >> 19) & 1) != 0)
889    }
890    #[doc = "Bit 20 - FLEXCOMM4 DATAOUT OUTPUT ENABLE"]
891    #[inline(always)]
892    pub fn fc4dataouten(&self) -> Fc4dataoutenR {
893        Fc4dataoutenR::new(((self.bits >> 20) & 1) != 0)
894    }
895    #[doc = "Bit 21 - FLEXCOMM5 DATAOUT OUTPUT ENABLE"]
896    #[inline(always)]
897    pub fn fc5dataouten(&self) -> Fc5dataoutenR {
898        Fc5dataoutenR::new(((self.bits >> 21) & 1) != 0)
899    }
900    #[doc = "Bit 22 - FLEXCOMM6 DATAOUT OUTPUT ENABLE"]
901    #[inline(always)]
902    pub fn fc6dataouten(&self) -> Fc6dataoutenR {
903        Fc6dataoutenR::new(((self.bits >> 22) & 1) != 0)
904    }
905    #[doc = "Bit 23 - FLEXCOMM7 DATAOUT OUTPUT ENABLE"]
906    #[inline(always)]
907    pub fn fc7dataouten(&self) -> Fc7dataoutenR {
908        Fc7dataoutenR::new(((self.bits >> 23) & 1) != 0)
909    }
910}
911#[cfg(feature = "debug")]
912impl core::fmt::Debug for R {
913    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
914        f.debug_struct("SHAREDCTRLSET")
915            .field("sharedscksel", &self.sharedscksel())
916            .field("sharedwssel", &self.sharedwssel())
917            .field("shareddatasel", &self.shareddatasel())
918            .field("fc0dataouten", &self.fc0dataouten())
919            .field("fc1dataouten", &self.fc1dataouten())
920            .field("f20dataouten", &self.f20dataouten())
921            .field("fc3dataouten", &self.fc3dataouten())
922            .field("fc4dataouten", &self.fc4dataouten())
923            .field("fc5dataouten", &self.fc5dataouten())
924            .field("fc6dataouten", &self.fc6dataouten())
925            .field("fc7dataouten", &self.fc7dataouten())
926            .finish()
927    }
928}
929impl W {
930    #[doc = "Bits 0:2 - Shared SCK Select. . ."]
931    #[inline(always)]
932    pub fn sharedscksel(&mut self) -> SharedsckselW<SharedctrlsetSpec> {
933        SharedsckselW::new(self, 0)
934    }
935    #[doc = "Bits 4:6 - Shared WS Select. . ."]
936    #[inline(always)]
937    pub fn sharedwssel(&mut self) -> SharedwsselW<SharedctrlsetSpec> {
938        SharedwsselW::new(self, 4)
939    }
940    #[doc = "Bits 8:10 - Shared DATA Select. . ."]
941    #[inline(always)]
942    pub fn shareddatasel(&mut self) -> ShareddataselW<SharedctrlsetSpec> {
943        ShareddataselW::new(self, 8)
944    }
945    #[doc = "Bit 16 - FLEXCOMM0 DATAOUT OUTPUT ENABLE"]
946    #[inline(always)]
947    pub fn fc0dataouten(&mut self) -> Fc0dataoutenW<SharedctrlsetSpec> {
948        Fc0dataoutenW::new(self, 16)
949    }
950    #[doc = "Bit 17 - FLEXCOMM1 DATAOUT OUTPUT ENABLE"]
951    #[inline(always)]
952    pub fn fc1dataouten(&mut self) -> Fc1dataoutenW<SharedctrlsetSpec> {
953        Fc1dataoutenW::new(self, 17)
954    }
955    #[doc = "Bit 18 - FLEXCOMM2 DATAOUT OUTPUT ENABLE"]
956    #[inline(always)]
957    pub fn f20dataouten(&mut self) -> F20dataoutenW<SharedctrlsetSpec> {
958        F20dataoutenW::new(self, 18)
959    }
960    #[doc = "Bit 19 - FLEXCOMM3 DATAOUT OUTPUT ENABLE"]
961    #[inline(always)]
962    pub fn fc3dataouten(&mut self) -> Fc3dataoutenW<SharedctrlsetSpec> {
963        Fc3dataoutenW::new(self, 19)
964    }
965    #[doc = "Bit 20 - FLEXCOMM4 DATAOUT OUTPUT ENABLE"]
966    #[inline(always)]
967    pub fn fc4dataouten(&mut self) -> Fc4dataoutenW<SharedctrlsetSpec> {
968        Fc4dataoutenW::new(self, 20)
969    }
970    #[doc = "Bit 21 - FLEXCOMM5 DATAOUT OUTPUT ENABLE"]
971    #[inline(always)]
972    pub fn fc5dataouten(&mut self) -> Fc5dataoutenW<SharedctrlsetSpec> {
973        Fc5dataoutenW::new(self, 21)
974    }
975    #[doc = "Bit 22 - FLEXCOMM6 DATAOUT OUTPUT ENABLE"]
976    #[inline(always)]
977    pub fn fc6dataouten(&mut self) -> Fc6dataoutenW<SharedctrlsetSpec> {
978        Fc6dataoutenW::new(self, 22)
979    }
980    #[doc = "Bit 23 - FLEXCOMM7 DATAOUT OUTPUT ENABLE"]
981    #[inline(always)]
982    pub fn fc7dataouten(&mut self) -> Fc7dataoutenW<SharedctrlsetSpec> {
983        Fc7dataoutenW::new(self, 23)
984    }
985}
986#[doc = "shared control set N\n\nYou can [`read`](crate::Reg::read) this register and get [`sharedctrlset::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sharedctrlset::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
987pub struct SharedctrlsetSpec;
988impl crate::RegisterSpec for SharedctrlsetSpec {
989    type Ux = u32;
990}
991#[doc = "`read()` method returns [`sharedctrlset::R`](R) reader structure"]
992impl crate::Readable for SharedctrlsetSpec {}
993#[doc = "`write(|w| ..)` method takes [`sharedctrlset::W`](W) writer structure"]
994impl crate::Writable for SharedctrlsetSpec {
995    type Safety = crate::Unsafe;
996    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
997    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
998}
999#[doc = "`reset()` method sets SHAREDCTRLSET%s to value 0"]
1000impl crate::Resettable for SharedctrlsetSpec {
1001    const RESET_VALUE: u32 = 0;
1002}
mimxrt685s_pac/sysctl1/sharedctrlset.rs

mimxrt685s_pac/sysctl1/
sharedctrlset.rs
