mimxrt685s_pac/
sysctl1.rs

1#[repr(C)]
2#[cfg_attr(feature = "debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    _reserved0: [u8; 0x10],
6    mclkpindir: Mclkpindir,
7    _reserved1: [u8; 0x1c],
8    dspnmisrcsel: Dspnmisrcsel,
9    _reserved2: [u8; 0x0c],
10    fcctrlsel: [Fcctrlsel; 8],
11    _reserved3: [u8; 0x20],
12    sharedctrlset: [Sharedctrlset; 2],
13    _reserved4: [u8; 0x0178],
14    rxevpulsegen: Rxevpulsegen,
15}
16impl RegisterBlock {
17    #[doc = "0x10 - mclk direction control"]
18    #[inline(always)]
19    pub const fn mclkpindir(&self) -> &Mclkpindir {
20        &self.mclkpindir
21    }
22    #[doc = "0x30 - DSP NMI source selection"]
23    #[inline(always)]
24    pub const fn dspnmisrcsel(&self) -> &Dspnmisrcsel {
25        &self.dspnmisrcsel
26    }
27    #[doc = "0x40..0x60 - flexcomm control selection N"]
28    #[inline(always)]
29    pub const fn fcctrlsel(&self, n: usize) -> &Fcctrlsel {
30        &self.fcctrlsel[n]
31    }
32    #[doc = "Iterator for array of:"]
33    #[doc = "0x40..0x60 - flexcomm control selection N"]
34    #[inline(always)]
35    pub fn fcctrlsel_iter(&self) -> impl Iterator<Item = &Fcctrlsel> {
36        self.fcctrlsel.iter()
37    }
38    #[doc = "0x80..0x88 - shared control set N"]
39    #[inline(always)]
40    pub const fn sharedctrlset(&self, n: usize) -> &Sharedctrlset {
41        &self.sharedctrlset[n]
42    }
43    #[doc = "Iterator for array of:"]
44    #[doc = "0x80..0x88 - shared control set N"]
45    #[inline(always)]
46    pub fn sharedctrlset_iter(&self) -> impl Iterator<Item = &Sharedctrlset> {
47        self.sharedctrlset.iter()
48    }
49    #[doc = "0x200 - RX Event Pulse Generator"]
50    #[inline(always)]
51    pub const fn rxevpulsegen(&self) -> &Rxevpulsegen {
52        &self.rxevpulsegen
53    }
54}
55#[doc = "MCLKPINDIR (rw) register accessor: mclk direction control\n\nYou can [`read`](crate::Reg::read) this register and get [`mclkpindir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mclkpindir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mclkpindir`]
56module"]
57#[doc(alias = "MCLKPINDIR")]
58pub type Mclkpindir = crate::Reg<mclkpindir::MclkpindirSpec>;
59#[doc = "mclk direction control"]
60pub mod mclkpindir;
61#[doc = "DSPNMISRCSEL (rw) register accessor: DSP NMI source selection\n\nYou can [`read`](crate::Reg::read) this register and get [`dspnmisrcsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dspnmisrcsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dspnmisrcsel`]
62module"]
63#[doc(alias = "DSPNMISRCSEL")]
64pub type Dspnmisrcsel = crate::Reg<dspnmisrcsel::DspnmisrcselSpec>;
65#[doc = "DSP NMI source selection"]
66pub mod dspnmisrcsel;
67#[doc = "FCCTRLSEL (rw) register accessor: flexcomm control selection N\n\nYou can [`read`](crate::Reg::read) this register and get [`fcctrlsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fcctrlsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcctrlsel`]
68module"]
69#[doc(alias = "FCCTRLSEL")]
70pub type Fcctrlsel = crate::Reg<fcctrlsel::FcctrlselSpec>;
71#[doc = "flexcomm control selection N"]
72pub mod fcctrlsel;
73#[doc = "SHAREDCTRLSET (rw) register accessor: shared control set N\n\nYou can [`read`](crate::Reg::read) this register and get [`sharedctrlset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sharedctrlset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sharedctrlset`]
74module"]
75#[doc(alias = "SHAREDCTRLSET")]
76pub type Sharedctrlset = crate::Reg<sharedctrlset::SharedctrlsetSpec>;
77#[doc = "shared control set N"]
78pub mod sharedctrlset;
79#[doc = "RXEVPULSEGEN (rw) register accessor: RX Event Pulse Generator\n\nYou can [`read`](crate::Reg::read) this register and get [`rxevpulsegen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxevpulsegen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxevpulsegen`]
80module"]
81#[doc(alias = "RXEVPULSEGEN")]
82pub type Rxevpulsegen = crate::Reg<rxevpulsegen::RxevpulsegenSpec>;
83#[doc = "RX Event Pulse Generator"]
84pub mod rxevpulsegen;
mimxrt685s_pac/sysctl1.rs

mimxrt685s_pac/
sysctl1.rs
