1#[doc = "Register `USBCLKCTRL` reader"]
2pub type R = crate::R<UsbclkctrlSpec>;
3#[doc = "Register `USBCLKCTRL` writer"]
4pub type W = crate::W<UsbclkctrlSpec>;
5#[doc = "USB0 Device need clock signal control\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum ApDevClk {
9 #[doc = "0: Under hardware control."]
10 UnderHwCtrl = 0,
11 #[doc = "1: Forced high."]
12 ForcedHigh = 1,
13}
14impl From<ApDevClk> for bool {
15 #[inline(always)]
16 fn from(variant: ApDevClk) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `AP_DEV_CLK` reader - USB0 Device need clock signal control"]
21pub type ApDevClkR = crate::BitReader<ApDevClk>;
22impl ApDevClkR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> ApDevClk {
26 match self.bits {
27 false => ApDevClk::UnderHwCtrl,
28 true => ApDevClk::ForcedHigh,
29 }
30 }
31 #[doc = "Under hardware control."]
32 #[inline(always)]
33 pub fn is_under_hw_ctrl(&self) -> bool {
34 *self == ApDevClk::UnderHwCtrl
35 }
36 #[doc = "Forced high."]
37 #[inline(always)]
38 pub fn is_forced_high(&self) -> bool {
39 *self == ApDevClk::ForcedHigh
40 }
41}
42#[doc = "Field `AP_DEV_CLK` writer - USB0 Device need clock signal control"]
43pub type ApDevClkW<'a, REG> = crate::BitWriter<'a, REG, ApDevClk>;
44impl<'a, REG> ApDevClkW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "Under hardware control."]
49 #[inline(always)]
50 pub fn under_hw_ctrl(self) -> &'a mut crate::W<REG> {
51 self.variant(ApDevClk::UnderHwCtrl)
52 }
53 #[doc = "Forced high."]
54 #[inline(always)]
55 pub fn forced_high(self) -> &'a mut crate::W<REG> {
56 self.variant(ApDevClk::ForcedHigh)
57 }
58}
59#[doc = "USB0 Device need clock polarity for triggering the USB1 wake-up interrupt\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum PolDevClk {
63 #[doc = "0: Falling edge of device need_clock triggers wake-up."]
64 FallingEdge = 0,
65 #[doc = "1: Rising edge of device need_clock triggers wake-up."]
66 RisingEdge = 1,
67}
68impl From<PolDevClk> for bool {
69 #[inline(always)]
70 fn from(variant: PolDevClk) -> Self {
71 variant as u8 != 0
72 }
73}
74#[doc = "Field `POL_DEV_CLK` reader - USB0 Device need clock polarity for triggering the USB1 wake-up interrupt"]
75pub type PolDevClkR = crate::BitReader<PolDevClk>;
76impl PolDevClkR {
77 #[doc = "Get enumerated values variant"]
78 #[inline(always)]
79 pub const fn variant(&self) -> PolDevClk {
80 match self.bits {
81 false => PolDevClk::FallingEdge,
82 true => PolDevClk::RisingEdge,
83 }
84 }
85 #[doc = "Falling edge of device need_clock triggers wake-up."]
86 #[inline(always)]
87 pub fn is_falling_edge(&self) -> bool {
88 *self == PolDevClk::FallingEdge
89 }
90 #[doc = "Rising edge of device need_clock triggers wake-up."]
91 #[inline(always)]
92 pub fn is_rising_edge(&self) -> bool {
93 *self == PolDevClk::RisingEdge
94 }
95}
96#[doc = "Field `POL_DEV_CLK` writer - USB0 Device need clock polarity for triggering the USB1 wake-up interrupt"]
97pub type PolDevClkW<'a, REG> = crate::BitWriter<'a, REG, PolDevClk>;
98impl<'a, REG> PolDevClkW<'a, REG>
99where
100 REG: crate::Writable + crate::RegisterSpec,
101{
102 #[doc = "Falling edge of device need_clock triggers wake-up."]
103 #[inline(always)]
104 pub fn falling_edge(self) -> &'a mut crate::W<REG> {
105 self.variant(PolDevClk::FallingEdge)
106 }
107 #[doc = "Rising edge of device need_clock triggers wake-up."]
108 #[inline(always)]
109 pub fn rising_edge(self) -> &'a mut crate::W<REG> {
110 self.variant(PolDevClk::RisingEdge)
111 }
112}
113#[doc = "USB0 Host need clock signal control\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum ApHostClk {
117 #[doc = "0: Under hardware control."]
118 UnderHwCtrl = 0,
119 #[doc = "1: Forced high."]
120 ForcedHigh = 1,
121}
122impl From<ApHostClk> for bool {
123 #[inline(always)]
124 fn from(variant: ApHostClk) -> Self {
125 variant as u8 != 0
126 }
127}
128#[doc = "Field `AP_HOST_CLK` reader - USB0 Host need clock signal control"]
129pub type ApHostClkR = crate::BitReader<ApHostClk>;
130impl ApHostClkR {
131 #[doc = "Get enumerated values variant"]
132 #[inline(always)]
133 pub const fn variant(&self) -> ApHostClk {
134 match self.bits {
135 false => ApHostClk::UnderHwCtrl,
136 true => ApHostClk::ForcedHigh,
137 }
138 }
139 #[doc = "Under hardware control."]
140 #[inline(always)]
141 pub fn is_under_hw_ctrl(&self) -> bool {
142 *self == ApHostClk::UnderHwCtrl
143 }
144 #[doc = "Forced high."]
145 #[inline(always)]
146 pub fn is_forced_high(&self) -> bool {
147 *self == ApHostClk::ForcedHigh
148 }
149}
150#[doc = "Field `AP_HOST_CLK` writer - USB0 Host need clock signal control"]
151pub type ApHostClkW<'a, REG> = crate::BitWriter<'a, REG, ApHostClk>;
152impl<'a, REG> ApHostClkW<'a, REG>
153where
154 REG: crate::Writable + crate::RegisterSpec,
155{
156 #[doc = "Under hardware control."]
157 #[inline(always)]
158 pub fn under_hw_ctrl(self) -> &'a mut crate::W<REG> {
159 self.variant(ApHostClk::UnderHwCtrl)
160 }
161 #[doc = "Forced high."]
162 #[inline(always)]
163 pub fn forced_high(self) -> &'a mut crate::W<REG> {
164 self.variant(ApHostClk::ForcedHigh)
165 }
166}
167#[doc = "USB0 HOST need clock polarity for triggering the USB1 wake-up interrupt\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum PolHostClk {
171 #[doc = "0: Falling edge of host need_clock triggers wake-up."]
172 FallingEdge = 0,
173 #[doc = "1: Rising edge of host need_clock triggers wake-up."]
174 RisingEdge = 1,
175}
176impl From<PolHostClk> for bool {
177 #[inline(always)]
178 fn from(variant: PolHostClk) -> Self {
179 variant as u8 != 0
180 }
181}
182#[doc = "Field `POL_HOST_CLK` reader - USB0 HOST need clock polarity for triggering the USB1 wake-up interrupt"]
183pub type PolHostClkR = crate::BitReader<PolHostClk>;
184impl PolHostClkR {
185 #[doc = "Get enumerated values variant"]
186 #[inline(always)]
187 pub const fn variant(&self) -> PolHostClk {
188 match self.bits {
189 false => PolHostClk::FallingEdge,
190 true => PolHostClk::RisingEdge,
191 }
192 }
193 #[doc = "Falling edge of host need_clock triggers wake-up."]
194 #[inline(always)]
195 pub fn is_falling_edge(&self) -> bool {
196 *self == PolHostClk::FallingEdge
197 }
198 #[doc = "Rising edge of host need_clock triggers wake-up."]
199 #[inline(always)]
200 pub fn is_rising_edge(&self) -> bool {
201 *self == PolHostClk::RisingEdge
202 }
203}
204#[doc = "Field `POL_HOST_CLK` writer - USB0 HOST need clock polarity for triggering the USB1 wake-up interrupt"]
205pub type PolHostClkW<'a, REG> = crate::BitWriter<'a, REG, PolHostClk>;
206impl<'a, REG> PolHostClkW<'a, REG>
207where
208 REG: crate::Writable + crate::RegisterSpec,
209{
210 #[doc = "Falling edge of host need_clock triggers wake-up."]
211 #[inline(always)]
212 pub fn falling_edge(self) -> &'a mut crate::W<REG> {
213 self.variant(PolHostClk::FallingEdge)
214 }
215 #[doc = "Rising edge of host need_clock triggers wake-up."]
216 #[inline(always)]
217 pub fn rising_edge(self) -> &'a mut crate::W<REG> {
218 self.variant(PolHostClk::RisingEdge)
219 }
220}
221#[doc = "External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic\n\nValue on reset: 1"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum HsDevWakeupN {
225 #[doc = "0: Forces USB0 PHY to wake-up."]
226 ForceToWakeup = 0,
227 #[doc = "1: Normal USB0 PHY behavior."]
228 Normal = 1,
229}
230impl From<HsDevWakeupN> for bool {
231 #[inline(always)]
232 fn from(variant: HsDevWakeupN) -> Self {
233 variant as u8 != 0
234 }
235}
236#[doc = "Field `HS_DEV_WAKEUP_N` reader - External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic"]
237pub type HsDevWakeupNR = crate::BitReader<HsDevWakeupN>;
238impl HsDevWakeupNR {
239 #[doc = "Get enumerated values variant"]
240 #[inline(always)]
241 pub const fn variant(&self) -> HsDevWakeupN {
242 match self.bits {
243 false => HsDevWakeupN::ForceToWakeup,
244 true => HsDevWakeupN::Normal,
245 }
246 }
247 #[doc = "Forces USB0 PHY to wake-up."]
248 #[inline(always)]
249 pub fn is_force_to_wakeup(&self) -> bool {
250 *self == HsDevWakeupN::ForceToWakeup
251 }
252 #[doc = "Normal USB0 PHY behavior."]
253 #[inline(always)]
254 pub fn is_normal(&self) -> bool {
255 *self == HsDevWakeupN::Normal
256 }
257}
258#[doc = "Field `HS_DEV_WAKEUP_N` writer - External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic"]
259pub type HsDevWakeupNW<'a, REG> = crate::BitWriter<'a, REG, HsDevWakeupN>;
260impl<'a, REG> HsDevWakeupNW<'a, REG>
261where
262 REG: crate::Writable + crate::RegisterSpec,
263{
264 #[doc = "Forces USB0 PHY to wake-up."]
265 #[inline(always)]
266 pub fn force_to_wakeup(self) -> &'a mut crate::W<REG> {
267 self.variant(HsDevWakeupN::ForceToWakeup)
268 }
269 #[doc = "Normal USB0 PHY behavior."]
270 #[inline(always)]
271 pub fn normal(self) -> &'a mut crate::W<REG> {
272 self.variant(HsDevWakeupN::Normal)
273 }
274}
275impl R {
276 #[doc = "Bit 0 - USB0 Device need clock signal control"]
277 #[inline(always)]
278 pub fn ap_dev_clk(&self) -> ApDevClkR {
279 ApDevClkR::new((self.bits & 1) != 0)
280 }
281 #[doc = "Bit 1 - USB0 Device need clock polarity for triggering the USB1 wake-up interrupt"]
282 #[inline(always)]
283 pub fn pol_dev_clk(&self) -> PolDevClkR {
284 PolDevClkR::new(((self.bits >> 1) & 1) != 0)
285 }
286 #[doc = "Bit 2 - USB0 Host need clock signal control"]
287 #[inline(always)]
288 pub fn ap_host_clk(&self) -> ApHostClkR {
289 ApHostClkR::new(((self.bits >> 2) & 1) != 0)
290 }
291 #[doc = "Bit 3 - USB0 HOST need clock polarity for triggering the USB1 wake-up interrupt"]
292 #[inline(always)]
293 pub fn pol_host_clk(&self) -> PolHostClkR {
294 PolHostClkR::new(((self.bits >> 3) & 1) != 0)
295 }
296 #[doc = "Bit 4 - External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic"]
297 #[inline(always)]
298 pub fn hs_dev_wakeup_n(&self) -> HsDevWakeupNR {
299 HsDevWakeupNR::new(((self.bits >> 4) & 1) != 0)
300 }
301}
302#[cfg(feature = "debug")]
303impl core::fmt::Debug for R {
304 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
305 f.debug_struct("USBCLKCTRL")
306 .field("ap_dev_clk", &self.ap_dev_clk())
307 .field("pol_dev_clk", &self.pol_dev_clk())
308 .field("ap_host_clk", &self.ap_host_clk())
309 .field("pol_host_clk", &self.pol_host_clk())
310 .field("hs_dev_wakeup_n", &self.hs_dev_wakeup_n())
311 .finish()
312 }
313}
314impl W {
315 #[doc = "Bit 0 - USB0 Device need clock signal control"]
316 #[inline(always)]
317 pub fn ap_dev_clk(&mut self) -> ApDevClkW<UsbclkctrlSpec> {
318 ApDevClkW::new(self, 0)
319 }
320 #[doc = "Bit 1 - USB0 Device need clock polarity for triggering the USB1 wake-up interrupt"]
321 #[inline(always)]
322 pub fn pol_dev_clk(&mut self) -> PolDevClkW<UsbclkctrlSpec> {
323 PolDevClkW::new(self, 1)
324 }
325 #[doc = "Bit 2 - USB0 Host need clock signal control"]
326 #[inline(always)]
327 pub fn ap_host_clk(&mut self) -> ApHostClkW<UsbclkctrlSpec> {
328 ApHostClkW::new(self, 2)
329 }
330 #[doc = "Bit 3 - USB0 HOST need clock polarity for triggering the USB1 wake-up interrupt"]
331 #[inline(always)]
332 pub fn pol_host_clk(&mut self) -> PolHostClkW<UsbclkctrlSpec> {
333 PolHostClkW::new(self, 3)
334 }
335 #[doc = "Bit 4 - External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to asynchronous control logic"]
336 #[inline(always)]
337 pub fn hs_dev_wakeup_n(&mut self) -> HsDevWakeupNW<UsbclkctrlSpec> {
338 HsDevWakeupNW::new(self, 4)
339 }
340}
341#[doc = "USB clock control\n\nYou can [`read`](crate::Reg::read) this register and get [`usbclkctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbclkctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
342pub struct UsbclkctrlSpec;
343impl crate::RegisterSpec for UsbclkctrlSpec {
344 type Ux = u32;
345}
346#[doc = "`read()` method returns [`usbclkctrl::R`](R) reader structure"]
347impl crate::Readable for UsbclkctrlSpec {}
348#[doc = "`write(|w| ..)` method takes [`usbclkctrl::W`](W) writer structure"]
349impl crate::Writable for UsbclkctrlSpec {
350 type Safety = crate::Unsafe;
351 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
352 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
353}
354#[doc = "`reset()` method sets USBCLKCTRL to value 0x10"]
355impl crate::Resettable for UsbclkctrlSpec {
356 const RESET_VALUE: u32 = 0x10;
357}