mimxrt685s_pac/sysctl0/
pdruncfg1_clr.rs

1#[doc = "Register `PDRUNCFG1_CLR` writer"]
2pub type W = crate::W<Pdruncfg1ClrSpec>;
3#[doc = "Array power\n\nValue on reset: 0"]
4#[cfg_attr(feature = "defmt", derive(defmt::Format))]
5#[derive(Clone, Copy, Debug, PartialEq, Eq)]
6pub enum PqSramApd {
7    #[doc = "0: No effect"]
8    NoEffect = 0,
9    #[doc = "1: Clears the PDRUNCFG1 Bit"]
10    ClrPdruncfg1 = 1,
11}
12impl From<PqSramApd> for bool {
13    #[inline(always)]
14    fn from(variant: PqSramApd) -> Self {
15        variant as u8 != 0
16    }
17}
18#[doc = "Field `PQ_SRAM_APD` writer - Array power"]
19pub type PqSramApdW<'a, REG> = crate::BitWriter<'a, REG, PqSramApd>;
20impl<'a, REG> PqSramApdW<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    #[doc = "No effect"]
25    #[inline(always)]
26    pub fn no_effect(self) -> &'a mut crate::W<REG> {
27        self.variant(PqSramApd::NoEffect)
28    }
29    #[doc = "Clears the PDRUNCFG1 Bit"]
30    #[inline(always)]
31    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
32        self.variant(PqSramApd::ClrPdruncfg1)
33    }
34}
35#[doc = "Peiph power\n\nValue on reset: 0"]
36#[cfg_attr(feature = "defmt", derive(defmt::Format))]
37#[derive(Clone, Copy, Debug, PartialEq, Eq)]
38pub enum PqSramPpd {
39    #[doc = "0: No effect"]
40    NoEffect = 0,
41    #[doc = "1: Clears the PDRUNCFG1 Bit"]
42    ClrPdruncfg1 = 1,
43}
44impl From<PqSramPpd> for bool {
45    #[inline(always)]
46    fn from(variant: PqSramPpd) -> Self {
47        variant as u8 != 0
48    }
49}
50#[doc = "Field `PQ_SRAM_PPD` writer - Peiph power"]
51pub type PqSramPpdW<'a, REG> = crate::BitWriter<'a, REG, PqSramPpd>;
52impl<'a, REG> PqSramPpdW<'a, REG>
53where
54    REG: crate::Writable + crate::RegisterSpec,
55{
56    #[doc = "No effect"]
57    #[inline(always)]
58    pub fn no_effect(self) -> &'a mut crate::W<REG> {
59        self.variant(PqSramPpd::NoEffect)
60    }
61    #[doc = "Clears the PDRUNCFG1 Bit"]
62    #[inline(always)]
63    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
64        self.variant(PqSramPpd::ClrPdruncfg1)
65    }
66}
67#[doc = "Array power\n\nValue on reset: 0"]
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum FlexspiSramApd {
71    #[doc = "0: No effect"]
72    NoEffect = 0,
73    #[doc = "1: Clears the PDRUNCFG1 Bit"]
74    ClrPdruncfg1 = 1,
75}
76impl From<FlexspiSramApd> for bool {
77    #[inline(always)]
78    fn from(variant: FlexspiSramApd) -> Self {
79        variant as u8 != 0
80    }
81}
82#[doc = "Field `FLEXSPI_SRAM_APD` writer - Array power"]
83pub type FlexspiSramApdW<'a, REG> = crate::BitWriter<'a, REG, FlexspiSramApd>;
84impl<'a, REG> FlexspiSramApdW<'a, REG>
85where
86    REG: crate::Writable + crate::RegisterSpec,
87{
88    #[doc = "No effect"]
89    #[inline(always)]
90    pub fn no_effect(self) -> &'a mut crate::W<REG> {
91        self.variant(FlexspiSramApd::NoEffect)
92    }
93    #[doc = "Clears the PDRUNCFG1 Bit"]
94    #[inline(always)]
95    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
96        self.variant(FlexspiSramApd::ClrPdruncfg1)
97    }
98}
99#[doc = "Peiph power\n\nValue on reset: 0"]
100#[cfg_attr(feature = "defmt", derive(defmt::Format))]
101#[derive(Clone, Copy, Debug, PartialEq, Eq)]
102pub enum FlexspiSramPpd {
103    #[doc = "0: No effect"]
104    NoEffect = 0,
105    #[doc = "1: Clears the PDRUNCFG1 Bit"]
106    ClrPdruncfg1 = 1,
107}
108impl From<FlexspiSramPpd> for bool {
109    #[inline(always)]
110    fn from(variant: FlexspiSramPpd) -> Self {
111        variant as u8 != 0
112    }
113}
114#[doc = "Field `FLEXSPI_SRAM_PPD` writer - Peiph power"]
115pub type FlexspiSramPpdW<'a, REG> = crate::BitWriter<'a, REG, FlexspiSramPpd>;
116impl<'a, REG> FlexspiSramPpdW<'a, REG>
117where
118    REG: crate::Writable + crate::RegisterSpec,
119{
120    #[doc = "No effect"]
121    #[inline(always)]
122    pub fn no_effect(self) -> &'a mut crate::W<REG> {
123        self.variant(FlexspiSramPpd::NoEffect)
124    }
125    #[doc = "Clears the PDRUNCFG1 Bit"]
126    #[inline(always)]
127    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
128        self.variant(FlexspiSramPpd::ClrPdruncfg1)
129    }
130}
131#[doc = "Array power\n\nValue on reset: 0"]
132#[cfg_attr(feature = "defmt", derive(defmt::Format))]
133#[derive(Clone, Copy, Debug, PartialEq, Eq)]
134pub enum UsbhsSramApd {
135    #[doc = "0: No effect"]
136    NoEffect = 0,
137    #[doc = "1: Clears the PDRUNCFG1 Bit"]
138    ClrPdruncfg1 = 1,
139}
140impl From<UsbhsSramApd> for bool {
141    #[inline(always)]
142    fn from(variant: UsbhsSramApd) -> Self {
143        variant as u8 != 0
144    }
145}
146#[doc = "Field `USBHS_SRAM_APD` writer - Array power"]
147pub type UsbhsSramApdW<'a, REG> = crate::BitWriter<'a, REG, UsbhsSramApd>;
148impl<'a, REG> UsbhsSramApdW<'a, REG>
149where
150    REG: crate::Writable + crate::RegisterSpec,
151{
152    #[doc = "No effect"]
153    #[inline(always)]
154    pub fn no_effect(self) -> &'a mut crate::W<REG> {
155        self.variant(UsbhsSramApd::NoEffect)
156    }
157    #[doc = "Clears the PDRUNCFG1 Bit"]
158    #[inline(always)]
159    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
160        self.variant(UsbhsSramApd::ClrPdruncfg1)
161    }
162}
163#[doc = "Peiph power\n\nValue on reset: 0"]
164#[cfg_attr(feature = "defmt", derive(defmt::Format))]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum UsbhsSramPpd {
167    #[doc = "0: No effect"]
168    NoEffect = 0,
169    #[doc = "1: Clears the PDRUNCFG1 Bit"]
170    ClrPdruncfg1 = 1,
171}
172impl From<UsbhsSramPpd> for bool {
173    #[inline(always)]
174    fn from(variant: UsbhsSramPpd) -> Self {
175        variant as u8 != 0
176    }
177}
178#[doc = "Field `USBHS_SRAM_PPD` writer - Peiph power"]
179pub type UsbhsSramPpdW<'a, REG> = crate::BitWriter<'a, REG, UsbhsSramPpd>;
180impl<'a, REG> UsbhsSramPpdW<'a, REG>
181where
182    REG: crate::Writable + crate::RegisterSpec,
183{
184    #[doc = "No effect"]
185    #[inline(always)]
186    pub fn no_effect(self) -> &'a mut crate::W<REG> {
187        self.variant(UsbhsSramPpd::NoEffect)
188    }
189    #[doc = "Clears the PDRUNCFG1 Bit"]
190    #[inline(always)]
191    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
192        self.variant(UsbhsSramPpd::ClrPdruncfg1)
193    }
194}
195#[doc = "Array power\n\nValue on reset: 0"]
196#[cfg_attr(feature = "defmt", derive(defmt::Format))]
197#[derive(Clone, Copy, Debug, PartialEq, Eq)]
198pub enum Usdhc0SramApd {
199    #[doc = "0: No effect"]
200    NoEffect = 0,
201    #[doc = "1: Clears the PDRUNCFG1 Bit"]
202    ClrPdruncfg1 = 1,
203}
204impl From<Usdhc0SramApd> for bool {
205    #[inline(always)]
206    fn from(variant: Usdhc0SramApd) -> Self {
207        variant as u8 != 0
208    }
209}
210#[doc = "Field `USDHC0_SRAM_APD` writer - Array power"]
211pub type Usdhc0SramApdW<'a, REG> = crate::BitWriter<'a, REG, Usdhc0SramApd>;
212impl<'a, REG> Usdhc0SramApdW<'a, REG>
213where
214    REG: crate::Writable + crate::RegisterSpec,
215{
216    #[doc = "No effect"]
217    #[inline(always)]
218    pub fn no_effect(self) -> &'a mut crate::W<REG> {
219        self.variant(Usdhc0SramApd::NoEffect)
220    }
221    #[doc = "Clears the PDRUNCFG1 Bit"]
222    #[inline(always)]
223    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
224        self.variant(Usdhc0SramApd::ClrPdruncfg1)
225    }
226}
227#[doc = "Array power\n\nValue on reset: 0"]
228#[cfg_attr(feature = "defmt", derive(defmt::Format))]
229#[derive(Clone, Copy, Debug, PartialEq, Eq)]
230pub enum Usdhc0SramPpd {
231    #[doc = "0: No effect"]
232    NoEffect = 0,
233    #[doc = "1: Clears the PDRUNCFG1 Bit"]
234    ClrPdruncfg1 = 1,
235}
236impl From<Usdhc0SramPpd> for bool {
237    #[inline(always)]
238    fn from(variant: Usdhc0SramPpd) -> Self {
239        variant as u8 != 0
240    }
241}
242#[doc = "Field `USDHC0_SRAM_PPD` writer - Array power"]
243pub type Usdhc0SramPpdW<'a, REG> = crate::BitWriter<'a, REG, Usdhc0SramPpd>;
244impl<'a, REG> Usdhc0SramPpdW<'a, REG>
245where
246    REG: crate::Writable + crate::RegisterSpec,
247{
248    #[doc = "No effect"]
249    #[inline(always)]
250    pub fn no_effect(self) -> &'a mut crate::W<REG> {
251        self.variant(Usdhc0SramPpd::NoEffect)
252    }
253    #[doc = "Clears the PDRUNCFG1 Bit"]
254    #[inline(always)]
255    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
256        self.variant(Usdhc0SramPpd::ClrPdruncfg1)
257    }
258}
259#[doc = "Peiph power\n\nValue on reset: 0"]
260#[cfg_attr(feature = "defmt", derive(defmt::Format))]
261#[derive(Clone, Copy, Debug, PartialEq, Eq)]
262pub enum Usdhc1SramApd {
263    #[doc = "0: No effect"]
264    NoEffect = 0,
265    #[doc = "1: Clears the PDRUNCFG1 Bit"]
266    ClrPdruncfg1 = 1,
267}
268impl From<Usdhc1SramApd> for bool {
269    #[inline(always)]
270    fn from(variant: Usdhc1SramApd) -> Self {
271        variant as u8 != 0
272    }
273}
274#[doc = "Field `USDHC1_SRAM_APD` writer - Peiph power"]
275pub type Usdhc1SramApdW<'a, REG> = crate::BitWriter<'a, REG, Usdhc1SramApd>;
276impl<'a, REG> Usdhc1SramApdW<'a, REG>
277where
278    REG: crate::Writable + crate::RegisterSpec,
279{
280    #[doc = "No effect"]
281    #[inline(always)]
282    pub fn no_effect(self) -> &'a mut crate::W<REG> {
283        self.variant(Usdhc1SramApd::NoEffect)
284    }
285    #[doc = "Clears the PDRUNCFG1 Bit"]
286    #[inline(always)]
287    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
288        self.variant(Usdhc1SramApd::ClrPdruncfg1)
289    }
290}
291#[doc = "Peiph power\n\nValue on reset: 0"]
292#[cfg_attr(feature = "defmt", derive(defmt::Format))]
293#[derive(Clone, Copy, Debug, PartialEq, Eq)]
294pub enum Usdhc1SramPpd {
295    #[doc = "0: No effect"]
296    NoEffect = 0,
297    #[doc = "1: Clears the PDRUNCFG1 Bit"]
298    ClrPdruncfg1 = 1,
299}
300impl From<Usdhc1SramPpd> for bool {
301    #[inline(always)]
302    fn from(variant: Usdhc1SramPpd) -> Self {
303        variant as u8 != 0
304    }
305}
306#[doc = "Field `USDHC1_SRAM_PPD` writer - Peiph power"]
307pub type Usdhc1SramPpdW<'a, REG> = crate::BitWriter<'a, REG, Usdhc1SramPpd>;
308impl<'a, REG> Usdhc1SramPpdW<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "No effect"]
313    #[inline(always)]
314    pub fn no_effect(self) -> &'a mut crate::W<REG> {
315        self.variant(Usdhc1SramPpd::NoEffect)
316    }
317    #[doc = "Clears the PDRUNCFG1 Bit"]
318    #[inline(always)]
319    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
320        self.variant(Usdhc1SramPpd::ClrPdruncfg1)
321    }
322}
323#[doc = "Array power\n\nValue on reset: 0"]
324#[cfg_attr(feature = "defmt", derive(defmt::Format))]
325#[derive(Clone, Copy, Debug, PartialEq, Eq)]
326pub enum CasperSramApd {
327    #[doc = "0: No effect"]
328    NoEffect = 0,
329    #[doc = "1: Clears the PDRUNCFG1 Bit"]
330    ClrPdruncfg1 = 1,
331}
332impl From<CasperSramApd> for bool {
333    #[inline(always)]
334    fn from(variant: CasperSramApd) -> Self {
335        variant as u8 != 0
336    }
337}
338#[doc = "Field `CASPER_SRAM_APD` writer - Array power"]
339pub type CasperSramApdW<'a, REG> = crate::BitWriter<'a, REG, CasperSramApd>;
340impl<'a, REG> CasperSramApdW<'a, REG>
341where
342    REG: crate::Writable + crate::RegisterSpec,
343{
344    #[doc = "No effect"]
345    #[inline(always)]
346    pub fn no_effect(self) -> &'a mut crate::W<REG> {
347        self.variant(CasperSramApd::NoEffect)
348    }
349    #[doc = "Clears the PDRUNCFG1 Bit"]
350    #[inline(always)]
351    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
352        self.variant(CasperSramApd::ClrPdruncfg1)
353    }
354}
355#[doc = "Peiph power\n\nValue on reset: 0"]
356#[cfg_attr(feature = "defmt", derive(defmt::Format))]
357#[derive(Clone, Copy, Debug, PartialEq, Eq)]
358pub enum CasperSramPpd {
359    #[doc = "0: No effect"]
360    NoEffect = 0,
361    #[doc = "1: Clears the PDRUNCFG1 Bit"]
362    ClrPdruncfg1 = 1,
363}
364impl From<CasperSramPpd> for bool {
365    #[inline(always)]
366    fn from(variant: CasperSramPpd) -> Self {
367        variant as u8 != 0
368    }
369}
370#[doc = "Field `CASPER_SRAM_PPD` writer - Peiph power"]
371pub type CasperSramPpdW<'a, REG> = crate::BitWriter<'a, REG, CasperSramPpd>;
372impl<'a, REG> CasperSramPpdW<'a, REG>
373where
374    REG: crate::Writable + crate::RegisterSpec,
375{
376    #[doc = "No effect"]
377    #[inline(always)]
378    pub fn no_effect(self) -> &'a mut crate::W<REG> {
379        self.variant(CasperSramPpd::NoEffect)
380    }
381    #[doc = "Clears the PDRUNCFG1 Bit"]
382    #[inline(always)]
383    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
384        self.variant(CasperSramPpd::ClrPdruncfg1)
385    }
386}
387#[doc = "Array power\n\nValue on reset: 0"]
388#[cfg_attr(feature = "defmt", derive(defmt::Format))]
389#[derive(Clone, Copy, Debug, PartialEq, Eq)]
390pub enum DspcacheRegfApd {
391    #[doc = "0: No effect"]
392    NoEffect = 0,
393    #[doc = "1: Clears the PDRUNCFG1 Bit"]
394    ClrPdruncfg1 = 1,
395}
396impl From<DspcacheRegfApd> for bool {
397    #[inline(always)]
398    fn from(variant: DspcacheRegfApd) -> Self {
399        variant as u8 != 0
400    }
401}
402#[doc = "Field `DSPCACHE_REGF_APD` writer - Array power"]
403pub type DspcacheRegfApdW<'a, REG> = crate::BitWriter<'a, REG, DspcacheRegfApd>;
404impl<'a, REG> DspcacheRegfApdW<'a, REG>
405where
406    REG: crate::Writable + crate::RegisterSpec,
407{
408    #[doc = "No effect"]
409    #[inline(always)]
410    pub fn no_effect(self) -> &'a mut crate::W<REG> {
411        self.variant(DspcacheRegfApd::NoEffect)
412    }
413    #[doc = "Clears the PDRUNCFG1 Bit"]
414    #[inline(always)]
415    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
416        self.variant(DspcacheRegfApd::ClrPdruncfg1)
417    }
418}
419#[doc = "Peiph power\n\nValue on reset: 0"]
420#[cfg_attr(feature = "defmt", derive(defmt::Format))]
421#[derive(Clone, Copy, Debug, PartialEq, Eq)]
422pub enum DspcacheRegfPpd {
423    #[doc = "0: No effect"]
424    NoEffect = 0,
425    #[doc = "1: Clears the PDRUNCFG1 Bit"]
426    ClrPdruncfg1 = 1,
427}
428impl From<DspcacheRegfPpd> for bool {
429    #[inline(always)]
430    fn from(variant: DspcacheRegfPpd) -> Self {
431        variant as u8 != 0
432    }
433}
434#[doc = "Field `DSPCACHE_REGF_PPD` writer - Peiph power"]
435pub type DspcacheRegfPpdW<'a, REG> = crate::BitWriter<'a, REG, DspcacheRegfPpd>;
436impl<'a, REG> DspcacheRegfPpdW<'a, REG>
437where
438    REG: crate::Writable + crate::RegisterSpec,
439{
440    #[doc = "No effect"]
441    #[inline(always)]
442    pub fn no_effect(self) -> &'a mut crate::W<REG> {
443        self.variant(DspcacheRegfPpd::NoEffect)
444    }
445    #[doc = "Clears the PDRUNCFG1 Bit"]
446    #[inline(always)]
447    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
448        self.variant(DspcacheRegfPpd::ClrPdruncfg1)
449    }
450}
451#[doc = "Array power\n\nValue on reset: 0"]
452#[cfg_attr(feature = "defmt", derive(defmt::Format))]
453#[derive(Clone, Copy, Debug, PartialEq, Eq)]
454pub enum DsptcmRegfApd {
455    #[doc = "0: No effect"]
456    NoEffect = 0,
457    #[doc = "1: Clears the PDRUNCFG1 Bit"]
458    ClrPdruncfg1 = 1,
459}
460impl From<DsptcmRegfApd> for bool {
461    #[inline(always)]
462    fn from(variant: DsptcmRegfApd) -> Self {
463        variant as u8 != 0
464    }
465}
466#[doc = "Field `DSPTCM_REGF_APD` writer - Array power"]
467pub type DsptcmRegfApdW<'a, REG> = crate::BitWriter<'a, REG, DsptcmRegfApd>;
468impl<'a, REG> DsptcmRegfApdW<'a, REG>
469where
470    REG: crate::Writable + crate::RegisterSpec,
471{
472    #[doc = "No effect"]
473    #[inline(always)]
474    pub fn no_effect(self) -> &'a mut crate::W<REG> {
475        self.variant(DsptcmRegfApd::NoEffect)
476    }
477    #[doc = "Clears the PDRUNCFG1 Bit"]
478    #[inline(always)]
479    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
480        self.variant(DsptcmRegfApd::ClrPdruncfg1)
481    }
482}
483#[doc = "Peiph power\n\nValue on reset: 0"]
484#[cfg_attr(feature = "defmt", derive(defmt::Format))]
485#[derive(Clone, Copy, Debug, PartialEq, Eq)]
486pub enum DsptcmRegfPpd {
487    #[doc = "0: No effect"]
488    NoEffect = 0,
489    #[doc = "1: Clears the PDRUNCFG1 Bit"]
490    ClrPdruncfg1 = 1,
491}
492impl From<DsptcmRegfPpd> for bool {
493    #[inline(always)]
494    fn from(variant: DsptcmRegfPpd) -> Self {
495        variant as u8 != 0
496    }
497}
498#[doc = "Field `DSPTCM_REGF_PPD` writer - Peiph power"]
499pub type DsptcmRegfPpdW<'a, REG> = crate::BitWriter<'a, REG, DsptcmRegfPpd>;
500impl<'a, REG> DsptcmRegfPpdW<'a, REG>
501where
502    REG: crate::Writable + crate::RegisterSpec,
503{
504    #[doc = "No effect"]
505    #[inline(always)]
506    pub fn no_effect(self) -> &'a mut crate::W<REG> {
507        self.variant(DsptcmRegfPpd::NoEffect)
508    }
509    #[doc = "Clears the PDRUNCFG1 Bit"]
510    #[inline(always)]
511    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
512        self.variant(DsptcmRegfPpd::ClrPdruncfg1)
513    }
514}
515#[doc = "array power and periph power\n\nValue on reset: 0"]
516#[cfg_attr(feature = "defmt", derive(defmt::Format))]
517#[derive(Clone, Copy, Debug, PartialEq, Eq)]
518pub enum RomPd {
519    #[doc = "0: No effect"]
520    NoEffect = 0,
521    #[doc = "1: Clears the PDRUNCFG1 Bit"]
522    ClrPdruncfg1 = 1,
523}
524impl From<RomPd> for bool {
525    #[inline(always)]
526    fn from(variant: RomPd) -> Self {
527        variant as u8 != 0
528    }
529}
530#[doc = "Field `ROM_PD` writer - array power and periph power"]
531pub type RomPdW<'a, REG> = crate::BitWriter<'a, REG, RomPd>;
532impl<'a, REG> RomPdW<'a, REG>
533where
534    REG: crate::Writable + crate::RegisterSpec,
535{
536    #[doc = "No effect"]
537    #[inline(always)]
538    pub fn no_effect(self) -> &'a mut crate::W<REG> {
539        self.variant(RomPd::NoEffect)
540    }
541    #[doc = "Clears the PDRUNCFG1 Bit"]
542    #[inline(always)]
543    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
544        self.variant(RomPd::ClrPdruncfg1)
545    }
546}
547#[doc = "no description available\n\nValue on reset: 0"]
548#[cfg_attr(feature = "defmt", derive(defmt::Format))]
549#[derive(Clone, Copy, Debug, PartialEq, Eq)]
550pub enum SramSleep {
551    #[doc = "0: No effect"]
552    NoEffect = 0,
553    #[doc = "1: Clears the PDRUNCFG1 Bit"]
554    ClrPdruncfg1 = 1,
555}
556impl From<SramSleep> for bool {
557    #[inline(always)]
558    fn from(variant: SramSleep) -> Self {
559        variant as u8 != 0
560    }
561}
562#[doc = "Field `SRAM_SLEEP` writer - no description available"]
563pub type SramSleepW<'a, REG> = crate::BitWriter<'a, REG, SramSleep>;
564impl<'a, REG> SramSleepW<'a, REG>
565where
566    REG: crate::Writable + crate::RegisterSpec,
567{
568    #[doc = "No effect"]
569    #[inline(always)]
570    pub fn no_effect(self) -> &'a mut crate::W<REG> {
571        self.variant(SramSleep::NoEffect)
572    }
573    #[doc = "Clears the PDRUNCFG1 Bit"]
574    #[inline(always)]
575    pub fn clr_pdruncfg1(self) -> &'a mut crate::W<REG> {
576        self.variant(SramSleep::ClrPdruncfg1)
577    }
578}
579#[cfg(feature = "debug")]
580impl core::fmt::Debug for crate::generic::Reg<Pdruncfg1ClrSpec> {
581    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
582        write!(f, "(not readable)")
583    }
584}
585impl W {
586    #[doc = "Bit 0 - Array power"]
587    #[inline(always)]
588    pub fn pq_sram_apd(&mut self) -> PqSramApdW<Pdruncfg1ClrSpec> {
589        PqSramApdW::new(self, 0)
590    }
591    #[doc = "Bit 1 - Peiph power"]
592    #[inline(always)]
593    pub fn pq_sram_ppd(&mut self) -> PqSramPpdW<Pdruncfg1ClrSpec> {
594        PqSramPpdW::new(self, 1)
595    }
596    #[doc = "Bit 2 - Array power"]
597    #[inline(always)]
598    pub fn flexspi_sram_apd(&mut self) -> FlexspiSramApdW<Pdruncfg1ClrSpec> {
599        FlexspiSramApdW::new(self, 2)
600    }
601    #[doc = "Bit 3 - Peiph power"]
602    #[inline(always)]
603    pub fn flexspi_sram_ppd(&mut self) -> FlexspiSramPpdW<Pdruncfg1ClrSpec> {
604        FlexspiSramPpdW::new(self, 3)
605    }
606    #[doc = "Bit 4 - Array power"]
607    #[inline(always)]
608    pub fn usbhs_sram_apd(&mut self) -> UsbhsSramApdW<Pdruncfg1ClrSpec> {
609        UsbhsSramApdW::new(self, 4)
610    }
611    #[doc = "Bit 5 - Peiph power"]
612    #[inline(always)]
613    pub fn usbhs_sram_ppd(&mut self) -> UsbhsSramPpdW<Pdruncfg1ClrSpec> {
614        UsbhsSramPpdW::new(self, 5)
615    }
616    #[doc = "Bit 6 - Array power"]
617    #[inline(always)]
618    pub fn usdhc0_sram_apd(&mut self) -> Usdhc0SramApdW<Pdruncfg1ClrSpec> {
619        Usdhc0SramApdW::new(self, 6)
620    }
621    #[doc = "Bit 7 - Array power"]
622    #[inline(always)]
623    pub fn usdhc0_sram_ppd(&mut self) -> Usdhc0SramPpdW<Pdruncfg1ClrSpec> {
624        Usdhc0SramPpdW::new(self, 7)
625    }
626    #[doc = "Bit 8 - Peiph power"]
627    #[inline(always)]
628    pub fn usdhc1_sram_apd(&mut self) -> Usdhc1SramApdW<Pdruncfg1ClrSpec> {
629        Usdhc1SramApdW::new(self, 8)
630    }
631    #[doc = "Bit 9 - Peiph power"]
632    #[inline(always)]
633    pub fn usdhc1_sram_ppd(&mut self) -> Usdhc1SramPpdW<Pdruncfg1ClrSpec> {
634        Usdhc1SramPpdW::new(self, 9)
635    }
636    #[doc = "Bit 10 - Array power"]
637    #[inline(always)]
638    pub fn casper_sram_apd(&mut self) -> CasperSramApdW<Pdruncfg1ClrSpec> {
639        CasperSramApdW::new(self, 10)
640    }
641    #[doc = "Bit 11 - Peiph power"]
642    #[inline(always)]
643    pub fn casper_sram_ppd(&mut self) -> CasperSramPpdW<Pdruncfg1ClrSpec> {
644        CasperSramPpdW::new(self, 11)
645    }
646    #[doc = "Bit 24 - Array power"]
647    #[inline(always)]
648    pub fn dspcache_regf_apd(&mut self) -> DspcacheRegfApdW<Pdruncfg1ClrSpec> {
649        DspcacheRegfApdW::new(self, 24)
650    }
651    #[doc = "Bit 25 - Peiph power"]
652    #[inline(always)]
653    pub fn dspcache_regf_ppd(&mut self) -> DspcacheRegfPpdW<Pdruncfg1ClrSpec> {
654        DspcacheRegfPpdW::new(self, 25)
655    }
656    #[doc = "Bit 26 - Array power"]
657    #[inline(always)]
658    pub fn dsptcm_regf_apd(&mut self) -> DsptcmRegfApdW<Pdruncfg1ClrSpec> {
659        DsptcmRegfApdW::new(self, 26)
660    }
661    #[doc = "Bit 27 - Peiph power"]
662    #[inline(always)]
663    pub fn dsptcm_regf_ppd(&mut self) -> DsptcmRegfPpdW<Pdruncfg1ClrSpec> {
664        DsptcmRegfPpdW::new(self, 27)
665    }
666    #[doc = "Bit 28 - array power and periph power"]
667    #[inline(always)]
668    pub fn rom_pd(&mut self) -> RomPdW<Pdruncfg1ClrSpec> {
669        RomPdW::new(self, 28)
670    }
671    #[doc = "Bit 31 - no description available"]
672    #[inline(always)]
673    pub fn sram_sleep(&mut self) -> SramSleepW<Pdruncfg1ClrSpec> {
674        SramSleepW::new(self, 31)
675    }
676}
677#[doc = "Run configuration 1 clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pdruncfg1_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
678pub struct Pdruncfg1ClrSpec;
679impl crate::RegisterSpec for Pdruncfg1ClrSpec {
680    type Ux = u32;
681}
682#[doc = "`write(|w| ..)` method takes [`pdruncfg1_clr::W`](W) writer structure"]
683impl crate::Writable for Pdruncfg1ClrSpec {
684    type Safety = crate::Unsafe;
685    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
686    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
687}
688#[doc = "`reset()` method sets PDRUNCFG1_CLR to value 0"]
689impl crate::Resettable for Pdruncfg1ClrSpec {
690    const RESET_VALUE: u32 = 0;
691}
mimxrt685s_pac/sysctl0/pdruncfg1_clr.rs

mimxrt685s_pac/sysctl0/
pdruncfg1_clr.rs
