mimxrt685s_pac/sau/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Enable {
9    #[doc = "0: The SAU is disabled."]
10    Disabled = 0,
11    #[doc = "1: The SAU is enabled."]
12    Enabled = 1,
13}
14impl From<Enable> for bool {
15    #[inline(always)]
16    fn from(variant: Enable) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `ENABLE` reader - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region."]
21pub type EnableR = crate::BitReader<Enable>;
22impl EnableR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Enable {
26        match self.bits {
27            false => Enable::Disabled,
28            true => Enable::Enabled,
29        }
30    }
31    #[doc = "The SAU is disabled."]
32    #[inline(always)]
33    pub fn is_disabled(&self) -> bool {
34        *self == Enable::Disabled
35    }
36    #[doc = "The SAU is enabled."]
37    #[inline(always)]
38    pub fn is_enabled(&self) -> bool {
39        *self == Enable::Enabled
40    }
41}
42#[doc = "Field `ENABLE` writer - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region."]
43pub type EnableW<'a, REG> = crate::BitWriter<'a, REG, Enable>;
44impl<'a, REG> EnableW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "The SAU is disabled."]
49    #[inline(always)]
50    pub fn disabled(self) -> &'a mut crate::W<REG> {
51        self.variant(Enable::Disabled)
52    }
53    #[doc = "The SAU is enabled."]
54    #[inline(always)]
55    pub fn enabled(self) -> &'a mut crate::W<REG> {
56        self.variant(Enable::Enabled)
57    }
58}
59#[doc = "All Non-secure.\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Allns {
63    #[doc = "0: Memory is marked as Secure and is not Non-secure callable."]
64    SecuredMemory = 0,
65    #[doc = "1: Memory is marked as Non-secure."]
66    NonSecuredMemory = 1,
67}
68impl From<Allns> for bool {
69    #[inline(always)]
70    fn from(variant: Allns) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `ALLNS` reader - All Non-secure."]
75pub type AllnsR = crate::BitReader<Allns>;
76impl AllnsR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Allns {
80        match self.bits {
81            false => Allns::SecuredMemory,
82            true => Allns::NonSecuredMemory,
83        }
84    }
85    #[doc = "Memory is marked as Secure and is not Non-secure callable."]
86    #[inline(always)]
87    pub fn is_secured_memory(&self) -> bool {
88        *self == Allns::SecuredMemory
89    }
90    #[doc = "Memory is marked as Non-secure."]
91    #[inline(always)]
92    pub fn is_non_secured_memory(&self) -> bool {
93        *self == Allns::NonSecuredMemory
94    }
95}
96#[doc = "Field `ALLNS` writer - All Non-secure."]
97pub type AllnsW<'a, REG> = crate::BitWriter<'a, REG, Allns>;
98impl<'a, REG> AllnsW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Memory is marked as Secure and is not Non-secure callable."]
103    #[inline(always)]
104    pub fn secured_memory(self) -> &'a mut crate::W<REG> {
105        self.variant(Allns::SecuredMemory)
106    }
107    #[doc = "Memory is marked as Non-secure."]
108    #[inline(always)]
109    pub fn non_secured_memory(self) -> &'a mut crate::W<REG> {
110        self.variant(Allns::NonSecuredMemory)
111    }
112}
113impl R {
114    #[doc = "Bit 0 - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region."]
115    #[inline(always)]
116    pub fn enable(&self) -> EnableR {
117        EnableR::new((self.bits & 1) != 0)
118    }
119    #[doc = "Bit 1 - All Non-secure."]
120    #[inline(always)]
121    pub fn allns(&self) -> AllnsR {
122        AllnsR::new(((self.bits >> 1) & 1) != 0)
123    }
124}
125#[cfg(feature = "debug")]
126impl core::fmt::Debug for R {
127    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
128        f.debug_struct("CTRL")
129            .field("enable", &self.enable())
130            .field("allns", &self.allns())
131            .finish()
132    }
133}
134impl W {
135    #[doc = "Bit 0 - Enable. Enables the SAU. This bit is RAZ/WI when the Security Extension is implemented without an SAU region."]
136    #[inline(always)]
137    pub fn enable(&mut self) -> EnableW<CtrlSpec> {
138        EnableW::new(self, 0)
139    }
140    #[doc = "Bit 1 - All Non-secure."]
141    #[inline(always)]
142    pub fn allns(&mut self) -> AllnsW<CtrlSpec> {
143        AllnsW::new(self, 1)
144    }
145}
146#[doc = "Security Attribution Unit Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
147pub struct CtrlSpec;
148impl crate::RegisterSpec for CtrlSpec {
149    type Ux = u32;
150}
151#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
152impl crate::Readable for CtrlSpec {}
153#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
154impl crate::Writable for CtrlSpec {
155    type Safety = crate::Unsafe;
156    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
157    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
158}
159#[doc = "`reset()` method sets CTRL to value 0"]
160impl crate::Resettable for CtrlSpec {
161    const RESET_VALUE: u32 = 0;
162}
mimxrt685s_pac/sau/ctrl.rs

mimxrt685s_pac/sau/
ctrl.rs
