mimxrt685s_pac/inputmux/
sct0_in_sel.rs

1#[doc = "Register `SCT0_IN_SEL%s` reader"]
2pub type R = crate::R<Sct0InSelSpec>;
3#[doc = "Register `SCT0_IN_SEL%s` writer"]
4pub type W = crate::W<Sct0InSelSpec>;
5#[doc = "SCT0 Input(n) Selection. 24:1 Selection for each. . .\n\nValue on reset: 31"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum SctInSel {
10    #[doc = "0: SCT0_PIN_INP0"]
11    Sct0PinInp0 = 0,
12    #[doc = "1: SCT0_PIN_INP1"]
13    Sct0PinInp1 = 1,
14    #[doc = "2: SCT0_PIN_INP2"]
15    Sct0PinInp2 = 2,
16    #[doc = "3: SCT0_PIN_INP3"]
17    Sct0PinInp3 = 3,
18    #[doc = "4: SCT0_PIN_INP4"]
19    Sct0PinInp4 = 4,
20    #[doc = "5: SCT0_PIN_INP5"]
21    Sct0PinInp5 = 5,
22    #[doc = "6: SCT0_PIN_INP6"]
23    Sct0PinInp6 = 6,
24    #[doc = "7: SCT0_PIN_INP7"]
25    Sct0PinInp7 = 7,
26    #[doc = "8: CT32BIT0_MAT0"]
27    Ct32bit0Mat0 = 8,
28    #[doc = "9: CT32BIT1_MAT0"]
29    Ct32bit1Mat0 = 9,
30    #[doc = "10: CT32BIT2_MAT0"]
31    Ct32bit2Mat0 = 10,
32    #[doc = "11: CT32BIT3_MAT0"]
33    Ct32bit3Mat0 = 11,
34    #[doc = "12: CT32BIT4_MAT0"]
35    Ct32bit4Mat0 = 12,
36    #[doc = "13: ADCIRQ"]
37    Adcirq = 13,
38    #[doc = "14: GPIOINT_BMATCH"]
39    GpiointBmatch = 14,
40    #[doc = "15: USB1_FRAME_TOGGLE"]
41    Usb1FrameToggle = 15,
42    #[doc = "16: CMP0_OUT"]
43    Cmp0Out = 16,
44    #[doc = "17: SHARED I2S0_SCLK"]
45    SharedI2s0Sclk = 17,
46    #[doc = "18: SHARED I2S1_SCLK"]
47    SharedI2s1Sclk = 18,
48    #[doc = "19: SHARED I2S0_WS"]
49    SharedI2s0Ws = 19,
50    #[doc = "20: SHARED I2S1_WS"]
51    SharedI2s1Ws = 20,
52    #[doc = "21: MCLK"]
53    Mclk = 21,
54    #[doc = "22: ARM_TXEV"]
55    ArmTxev = 22,
56    #[doc = "23: DEBUG_HALTED"]
57    DebugHalted = 23,
58}
59impl From<SctInSel> for u8 {
60    #[inline(always)]
61    fn from(variant: SctInSel) -> Self {
62        variant as _
63    }
64}
65impl crate::FieldSpec for SctInSel {
66    type Ux = u8;
67}
68impl crate::IsEnum for SctInSel {}
69#[doc = "Field `SCT_IN_SEL` reader - SCT0 Input(n) Selection. 24:1 Selection for each. . ."]
70pub type SctInSelR = crate::FieldReader<SctInSel>;
71impl SctInSelR {
72    #[doc = "Get enumerated values variant"]
73    #[inline(always)]
74    pub const fn variant(&self) -> Option<SctInSel> {
75        match self.bits {
76            0 => Some(SctInSel::Sct0PinInp0),
77            1 => Some(SctInSel::Sct0PinInp1),
78            2 => Some(SctInSel::Sct0PinInp2),
79            3 => Some(SctInSel::Sct0PinInp3),
80            4 => Some(SctInSel::Sct0PinInp4),
81            5 => Some(SctInSel::Sct0PinInp5),
82            6 => Some(SctInSel::Sct0PinInp6),
83            7 => Some(SctInSel::Sct0PinInp7),
84            8 => Some(SctInSel::Ct32bit0Mat0),
85            9 => Some(SctInSel::Ct32bit1Mat0),
86            10 => Some(SctInSel::Ct32bit2Mat0),
87            11 => Some(SctInSel::Ct32bit3Mat0),
88            12 => Some(SctInSel::Ct32bit4Mat0),
89            13 => Some(SctInSel::Adcirq),
90            14 => Some(SctInSel::GpiointBmatch),
91            15 => Some(SctInSel::Usb1FrameToggle),
92            16 => Some(SctInSel::Cmp0Out),
93            17 => Some(SctInSel::SharedI2s0Sclk),
94            18 => Some(SctInSel::SharedI2s1Sclk),
95            19 => Some(SctInSel::SharedI2s0Ws),
96            20 => Some(SctInSel::SharedI2s1Ws),
97            21 => Some(SctInSel::Mclk),
98            22 => Some(SctInSel::ArmTxev),
99            23 => Some(SctInSel::DebugHalted),
100            _ => None,
101        }
102    }
103    #[doc = "SCT0_PIN_INP0"]
104    #[inline(always)]
105    pub fn is_sct0_pin_inp0(&self) -> bool {
106        *self == SctInSel::Sct0PinInp0
107    }
108    #[doc = "SCT0_PIN_INP1"]
109    #[inline(always)]
110    pub fn is_sct0_pin_inp1(&self) -> bool {
111        *self == SctInSel::Sct0PinInp1
112    }
113    #[doc = "SCT0_PIN_INP2"]
114    #[inline(always)]
115    pub fn is_sct0_pin_inp2(&self) -> bool {
116        *self == SctInSel::Sct0PinInp2
117    }
118    #[doc = "SCT0_PIN_INP3"]
119    #[inline(always)]
120    pub fn is_sct0_pin_inp3(&self) -> bool {
121        *self == SctInSel::Sct0PinInp3
122    }
123    #[doc = "SCT0_PIN_INP4"]
124    #[inline(always)]
125    pub fn is_sct0_pin_inp4(&self) -> bool {
126        *self == SctInSel::Sct0PinInp4
127    }
128    #[doc = "SCT0_PIN_INP5"]
129    #[inline(always)]
130    pub fn is_sct0_pin_inp5(&self) -> bool {
131        *self == SctInSel::Sct0PinInp5
132    }
133    #[doc = "SCT0_PIN_INP6"]
134    #[inline(always)]
135    pub fn is_sct0_pin_inp6(&self) -> bool {
136        *self == SctInSel::Sct0PinInp6
137    }
138    #[doc = "SCT0_PIN_INP7"]
139    #[inline(always)]
140    pub fn is_sct0_pin_inp7(&self) -> bool {
141        *self == SctInSel::Sct0PinInp7
142    }
143    #[doc = "CT32BIT0_MAT0"]
144    #[inline(always)]
145    pub fn is_ct32bit0_mat0(&self) -> bool {
146        *self == SctInSel::Ct32bit0Mat0
147    }
148    #[doc = "CT32BIT1_MAT0"]
149    #[inline(always)]
150    pub fn is_ct32bit1_mat0(&self) -> bool {
151        *self == SctInSel::Ct32bit1Mat0
152    }
153    #[doc = "CT32BIT2_MAT0"]
154    #[inline(always)]
155    pub fn is_ct32bit2_mat0(&self) -> bool {
156        *self == SctInSel::Ct32bit2Mat0
157    }
158    #[doc = "CT32BIT3_MAT0"]
159    #[inline(always)]
160    pub fn is_ct32bit3_mat0(&self) -> bool {
161        *self == SctInSel::Ct32bit3Mat0
162    }
163    #[doc = "CT32BIT4_MAT0"]
164    #[inline(always)]
165    pub fn is_ct32bit4_mat0(&self) -> bool {
166        *self == SctInSel::Ct32bit4Mat0
167    }
168    #[doc = "ADCIRQ"]
169    #[inline(always)]
170    pub fn is_adcirq(&self) -> bool {
171        *self == SctInSel::Adcirq
172    }
173    #[doc = "GPIOINT_BMATCH"]
174    #[inline(always)]
175    pub fn is_gpioint_bmatch(&self) -> bool {
176        *self == SctInSel::GpiointBmatch
177    }
178    #[doc = "USB1_FRAME_TOGGLE"]
179    #[inline(always)]
180    pub fn is_usb1_frame_toggle(&self) -> bool {
181        *self == SctInSel::Usb1FrameToggle
182    }
183    #[doc = "CMP0_OUT"]
184    #[inline(always)]
185    pub fn is_cmp0_out(&self) -> bool {
186        *self == SctInSel::Cmp0Out
187    }
188    #[doc = "SHARED I2S0_SCLK"]
189    #[inline(always)]
190    pub fn is_shared_i2s0_sclk(&self) -> bool {
191        *self == SctInSel::SharedI2s0Sclk
192    }
193    #[doc = "SHARED I2S1_SCLK"]
194    #[inline(always)]
195    pub fn is_shared_i2s1_sclk(&self) -> bool {
196        *self == SctInSel::SharedI2s1Sclk
197    }
198    #[doc = "SHARED I2S0_WS"]
199    #[inline(always)]
200    pub fn is_shared_i2s0_ws(&self) -> bool {
201        *self == SctInSel::SharedI2s0Ws
202    }
203    #[doc = "SHARED I2S1_WS"]
204    #[inline(always)]
205    pub fn is_shared_i2s1_ws(&self) -> bool {
206        *self == SctInSel::SharedI2s1Ws
207    }
208    #[doc = "MCLK"]
209    #[inline(always)]
210    pub fn is_mclk(&self) -> bool {
211        *self == SctInSel::Mclk
212    }
213    #[doc = "ARM_TXEV"]
214    #[inline(always)]
215    pub fn is_arm_txev(&self) -> bool {
216        *self == SctInSel::ArmTxev
217    }
218    #[doc = "DEBUG_HALTED"]
219    #[inline(always)]
220    pub fn is_debug_halted(&self) -> bool {
221        *self == SctInSel::DebugHalted
222    }
223}
224#[doc = "Field `SCT_IN_SEL` writer - SCT0 Input(n) Selection. 24:1 Selection for each. . ."]
225pub type SctInSelW<'a, REG> = crate::FieldWriter<'a, REG, 5, SctInSel>;
226impl<'a, REG> SctInSelW<'a, REG>
227where
228    REG: crate::Writable + crate::RegisterSpec,
229    REG::Ux: From<u8>,
230{
231    #[doc = "SCT0_PIN_INP0"]
232    #[inline(always)]
233    pub fn sct0_pin_inp0(self) -> &'a mut crate::W<REG> {
234        self.variant(SctInSel::Sct0PinInp0)
235    }
236    #[doc = "SCT0_PIN_INP1"]
237    #[inline(always)]
238    pub fn sct0_pin_inp1(self) -> &'a mut crate::W<REG> {
239        self.variant(SctInSel::Sct0PinInp1)
240    }
241    #[doc = "SCT0_PIN_INP2"]
242    #[inline(always)]
243    pub fn sct0_pin_inp2(self) -> &'a mut crate::W<REG> {
244        self.variant(SctInSel::Sct0PinInp2)
245    }
246    #[doc = "SCT0_PIN_INP3"]
247    #[inline(always)]
248    pub fn sct0_pin_inp3(self) -> &'a mut crate::W<REG> {
249        self.variant(SctInSel::Sct0PinInp3)
250    }
251    #[doc = "SCT0_PIN_INP4"]
252    #[inline(always)]
253    pub fn sct0_pin_inp4(self) -> &'a mut crate::W<REG> {
254        self.variant(SctInSel::Sct0PinInp4)
255    }
256    #[doc = "SCT0_PIN_INP5"]
257    #[inline(always)]
258    pub fn sct0_pin_inp5(self) -> &'a mut crate::W<REG> {
259        self.variant(SctInSel::Sct0PinInp5)
260    }
261    #[doc = "SCT0_PIN_INP6"]
262    #[inline(always)]
263    pub fn sct0_pin_inp6(self) -> &'a mut crate::W<REG> {
264        self.variant(SctInSel::Sct0PinInp6)
265    }
266    #[doc = "SCT0_PIN_INP7"]
267    #[inline(always)]
268    pub fn sct0_pin_inp7(self) -> &'a mut crate::W<REG> {
269        self.variant(SctInSel::Sct0PinInp7)
270    }
271    #[doc = "CT32BIT0_MAT0"]
272    #[inline(always)]
273    pub fn ct32bit0_mat0(self) -> &'a mut crate::W<REG> {
274        self.variant(SctInSel::Ct32bit0Mat0)
275    }
276    #[doc = "CT32BIT1_MAT0"]
277    #[inline(always)]
278    pub fn ct32bit1_mat0(self) -> &'a mut crate::W<REG> {
279        self.variant(SctInSel::Ct32bit1Mat0)
280    }
281    #[doc = "CT32BIT2_MAT0"]
282    #[inline(always)]
283    pub fn ct32bit2_mat0(self) -> &'a mut crate::W<REG> {
284        self.variant(SctInSel::Ct32bit2Mat0)
285    }
286    #[doc = "CT32BIT3_MAT0"]
287    #[inline(always)]
288    pub fn ct32bit3_mat0(self) -> &'a mut crate::W<REG> {
289        self.variant(SctInSel::Ct32bit3Mat0)
290    }
291    #[doc = "CT32BIT4_MAT0"]
292    #[inline(always)]
293    pub fn ct32bit4_mat0(self) -> &'a mut crate::W<REG> {
294        self.variant(SctInSel::Ct32bit4Mat0)
295    }
296    #[doc = "ADCIRQ"]
297    #[inline(always)]
298    pub fn adcirq(self) -> &'a mut crate::W<REG> {
299        self.variant(SctInSel::Adcirq)
300    }
301    #[doc = "GPIOINT_BMATCH"]
302    #[inline(always)]
303    pub fn gpioint_bmatch(self) -> &'a mut crate::W<REG> {
304        self.variant(SctInSel::GpiointBmatch)
305    }
306    #[doc = "USB1_FRAME_TOGGLE"]
307    #[inline(always)]
308    pub fn usb1_frame_toggle(self) -> &'a mut crate::W<REG> {
309        self.variant(SctInSel::Usb1FrameToggle)
310    }
311    #[doc = "CMP0_OUT"]
312    #[inline(always)]
313    pub fn cmp0_out(self) -> &'a mut crate::W<REG> {
314        self.variant(SctInSel::Cmp0Out)
315    }
316    #[doc = "SHARED I2S0_SCLK"]
317    #[inline(always)]
318    pub fn shared_i2s0_sclk(self) -> &'a mut crate::W<REG> {
319        self.variant(SctInSel::SharedI2s0Sclk)
320    }
321    #[doc = "SHARED I2S1_SCLK"]
322    #[inline(always)]
323    pub fn shared_i2s1_sclk(self) -> &'a mut crate::W<REG> {
324        self.variant(SctInSel::SharedI2s1Sclk)
325    }
326    #[doc = "SHARED I2S0_WS"]
327    #[inline(always)]
328    pub fn shared_i2s0_ws(self) -> &'a mut crate::W<REG> {
329        self.variant(SctInSel::SharedI2s0Ws)
330    }
331    #[doc = "SHARED I2S1_WS"]
332    #[inline(always)]
333    pub fn shared_i2s1_ws(self) -> &'a mut crate::W<REG> {
334        self.variant(SctInSel::SharedI2s1Ws)
335    }
336    #[doc = "MCLK"]
337    #[inline(always)]
338    pub fn mclk(self) -> &'a mut crate::W<REG> {
339        self.variant(SctInSel::Mclk)
340    }
341    #[doc = "ARM_TXEV"]
342    #[inline(always)]
343    pub fn arm_txev(self) -> &'a mut crate::W<REG> {
344        self.variant(SctInSel::ArmTxev)
345    }
346    #[doc = "DEBUG_HALTED"]
347    #[inline(always)]
348    pub fn debug_halted(self) -> &'a mut crate::W<REG> {
349        self.variant(SctInSel::DebugHalted)
350    }
351}
352impl R {
353    #[doc = "Bits 0:4 - SCT0 Input(n) Selection. 24:1 Selection for each. . ."]
354    #[inline(always)]
355    pub fn sct_in_sel(&self) -> SctInSelR {
356        SctInSelR::new((self.bits & 0x1f) as u8)
357    }
358}
359#[cfg(feature = "debug")]
360impl core::fmt::Debug for R {
361    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
362        f.debug_struct("SCT0_IN_SEL")
363            .field("sct_in_sel", &self.sct_in_sel())
364            .finish()
365    }
366}
367impl W {
368    #[doc = "Bits 0:4 - SCT0 Input(n) Selection. 24:1 Selection for each. . ."]
369    #[inline(always)]
370    pub fn sct_in_sel(&mut self) -> SctInSelW<Sct0InSelSpec> {
371        SctInSelW::new(self, 0)
372    }
373}
374#[doc = "SCT Peripheral Input Multiplexers N\n\nYou can [`read`](crate::Reg::read) this register and get [`sct0_in_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sct0_in_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
375pub struct Sct0InSelSpec;
376impl crate::RegisterSpec for Sct0InSelSpec {
377    type Ux = u32;
378}
379#[doc = "`read()` method returns [`sct0_in_sel::R`](R) reader structure"]
380impl crate::Readable for Sct0InSelSpec {}
381#[doc = "`write(|w| ..)` method takes [`sct0_in_sel::W`](W) writer structure"]
382impl crate::Writable for Sct0InSelSpec {
383    type Safety = crate::Unsafe;
384    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
385    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
386}
387#[doc = "`reset()` method sets SCT0_IN_SEL%s to value 0x1f"]
388impl crate::Resettable for Sct0InSelSpec {
389    const RESET_VALUE: u32 = 0x1f;
390}
mimxrt685s_pac/inputmux/sct0_in_sel.rs

mimxrt685s_pac/inputmux/
sct0_in_sel.rs
