mimxrt685s_pac/inputmux/
dsp_int_sel.rs

1#[doc = "Register `DSP_INT_SEL[%s]` reader"]
2pub type R = crate::R<DspIntSelSpec>;
3#[doc = "Register `DSP_INT_SEL[%s]` writer"]
4pub type W = crate::W<DspIntSelSpec>;
5#[doc = "DSP Input(n) Selection. 34:1 Selection for each. . .\n\nValue on reset: 63"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum DspIntSel {
10    #[doc = "0: FLEXCOMM0"]
11    Flexcomm0 = 0,
12    #[doc = "1: FLEXCOMM1"]
13    Flexcomm1 = 1,
14    #[doc = "2: FLEXCOMM2"]
15    Flexcomm2 = 2,
16    #[doc = "3: FLEXCOMM3"]
17    Flexcomm3 = 3,
18    #[doc = "4: FLEXCOMM4"]
19    Flexcomm4 = 4,
20    #[doc = "5: FLEXCOMM5"]
21    Flexcomm5 = 5,
22    #[doc = "6: FLEXCOMM6"]
23    Flexcomm6 = 6,
24    #[doc = "7: FLEXCOMM7"]
25    Flexcomm7 = 7,
26    #[doc = "8: GPIO_INT0_IRQ0"]
27    GpioInt0Irq0 = 8,
28    #[doc = "9: GPIO_INT0_IRQ1"]
29    GpioInt0Irq1 = 9,
30    #[doc = "10: GPIO_INT0_IRQ2"]
31    GpioInt0Irq2 = 10,
32    #[doc = "11: GPIO_INT0_IRQ3"]
33    GpioInt0Irq3 = 11,
34    #[doc = "12: GPIO_INT0_IRQ4"]
35    GpioInt0Irq4 = 12,
36    #[doc = "13: GPIO_INT0_IRQ5"]
37    GpioInt0Irq5 = 13,
38    #[doc = "14: GPIO_INT0_IRQ6"]
39    GpioInt0Irq6 = 14,
40    #[doc = "15: GPIO_INT0_IRQ7"]
41    GpioInt0Irq7 = 15,
42    #[doc = "16: NSHSGPIO_INT0"]
43    NshsgpioInt0 = 16,
44    #[doc = "17: NSHSGPIO_INT1"]
45    NshsgpioInt1 = 17,
46    #[doc = "18: WDT1"]
47    Wdt1 = 18,
48    #[doc = "19: DMAC0"]
49    Dmac0 = 19,
50    #[doc = "20: DMAC1"]
51    Dmac1 = 20,
52    #[doc = "21: MU"]
53    Mu = 21,
54    #[doc = "22: UTICK0"]
55    Utick0 = 22,
56    #[doc = "23: MRT0"]
57    Mrt0 = 23,
58    #[doc = "24: OS_EVENT_TIMER or OS_EVENT_WAKEUP"]
59    OsEventTimerOrOsEventWakeup = 24,
60    #[doc = "25: CT32BIT0"]
61    Ct32bit0 = 25,
62    #[doc = "26: CT32BIT1"]
63    Ct32bit1 = 26,
64    #[doc = "27: CT32BIT2"]
65    Ct32bit2 = 27,
66    #[doc = "28: CT32BIT3"]
67    Ct32bit3 = 28,
68    #[doc = "29: CT32BIT4"]
69    Ct32bit4 = 29,
70    #[doc = "30: RTC_LITE0_ALARM or RTC_LITE0_WAKEUP"]
71    RtcLite0AlarmOrRtcLite0Wakeup = 30,
72    #[doc = "31: I3C0"]
73    I3c0 = 31,
74    #[doc = "32: DMIC0"]
75    Dmic0 = 32,
76    #[doc = "33: HWVAD0"]
77    Hwvad0 = 33,
78    #[doc = "34: FLEXSPI"]
79    Flexspi = 34,
80}
81impl From<DspIntSel> for u8 {
82    #[inline(always)]
83    fn from(variant: DspIntSel) -> Self {
84        variant as _
85    }
86}
87impl crate::FieldSpec for DspIntSel {
88    type Ux = u8;
89}
90impl crate::IsEnum for DspIntSel {}
91#[doc = "Field `DSP_INT_SEL` reader - DSP Input(n) Selection. 34:1 Selection for each. . ."]
92pub type DspIntSelR = crate::FieldReader<DspIntSel>;
93impl DspIntSelR {
94    #[doc = "Get enumerated values variant"]
95    #[inline(always)]
96    pub const fn variant(&self) -> Option<DspIntSel> {
97        match self.bits {
98            0 => Some(DspIntSel::Flexcomm0),
99            1 => Some(DspIntSel::Flexcomm1),
100            2 => Some(DspIntSel::Flexcomm2),
101            3 => Some(DspIntSel::Flexcomm3),
102            4 => Some(DspIntSel::Flexcomm4),
103            5 => Some(DspIntSel::Flexcomm5),
104            6 => Some(DspIntSel::Flexcomm6),
105            7 => Some(DspIntSel::Flexcomm7),
106            8 => Some(DspIntSel::GpioInt0Irq0),
107            9 => Some(DspIntSel::GpioInt0Irq1),
108            10 => Some(DspIntSel::GpioInt0Irq2),
109            11 => Some(DspIntSel::GpioInt0Irq3),
110            12 => Some(DspIntSel::GpioInt0Irq4),
111            13 => Some(DspIntSel::GpioInt0Irq5),
112            14 => Some(DspIntSel::GpioInt0Irq6),
113            15 => Some(DspIntSel::GpioInt0Irq7),
114            16 => Some(DspIntSel::NshsgpioInt0),
115            17 => Some(DspIntSel::NshsgpioInt1),
116            18 => Some(DspIntSel::Wdt1),
117            19 => Some(DspIntSel::Dmac0),
118            20 => Some(DspIntSel::Dmac1),
119            21 => Some(DspIntSel::Mu),
120            22 => Some(DspIntSel::Utick0),
121            23 => Some(DspIntSel::Mrt0),
122            24 => Some(DspIntSel::OsEventTimerOrOsEventWakeup),
123            25 => Some(DspIntSel::Ct32bit0),
124            26 => Some(DspIntSel::Ct32bit1),
125            27 => Some(DspIntSel::Ct32bit2),
126            28 => Some(DspIntSel::Ct32bit3),
127            29 => Some(DspIntSel::Ct32bit4),
128            30 => Some(DspIntSel::RtcLite0AlarmOrRtcLite0Wakeup),
129            31 => Some(DspIntSel::I3c0),
130            32 => Some(DspIntSel::Dmic0),
131            33 => Some(DspIntSel::Hwvad0),
132            34 => Some(DspIntSel::Flexspi),
133            _ => None,
134        }
135    }
136    #[doc = "FLEXCOMM0"]
137    #[inline(always)]
138    pub fn is_flexcomm0(&self) -> bool {
139        *self == DspIntSel::Flexcomm0
140    }
141    #[doc = "FLEXCOMM1"]
142    #[inline(always)]
143    pub fn is_flexcomm1(&self) -> bool {
144        *self == DspIntSel::Flexcomm1
145    }
146    #[doc = "FLEXCOMM2"]
147    #[inline(always)]
148    pub fn is_flexcomm2(&self) -> bool {
149        *self == DspIntSel::Flexcomm2
150    }
151    #[doc = "FLEXCOMM3"]
152    #[inline(always)]
153    pub fn is_flexcomm3(&self) -> bool {
154        *self == DspIntSel::Flexcomm3
155    }
156    #[doc = "FLEXCOMM4"]
157    #[inline(always)]
158    pub fn is_flexcomm4(&self) -> bool {
159        *self == DspIntSel::Flexcomm4
160    }
161    #[doc = "FLEXCOMM5"]
162    #[inline(always)]
163    pub fn is_flexcomm5(&self) -> bool {
164        *self == DspIntSel::Flexcomm5
165    }
166    #[doc = "FLEXCOMM6"]
167    #[inline(always)]
168    pub fn is_flexcomm6(&self) -> bool {
169        *self == DspIntSel::Flexcomm6
170    }
171    #[doc = "FLEXCOMM7"]
172    #[inline(always)]
173    pub fn is_flexcomm7(&self) -> bool {
174        *self == DspIntSel::Flexcomm7
175    }
176    #[doc = "GPIO_INT0_IRQ0"]
177    #[inline(always)]
178    pub fn is_gpio_int0_irq0(&self) -> bool {
179        *self == DspIntSel::GpioInt0Irq0
180    }
181    #[doc = "GPIO_INT0_IRQ1"]
182    #[inline(always)]
183    pub fn is_gpio_int0_irq1(&self) -> bool {
184        *self == DspIntSel::GpioInt0Irq1
185    }
186    #[doc = "GPIO_INT0_IRQ2"]
187    #[inline(always)]
188    pub fn is_gpio_int0_irq2(&self) -> bool {
189        *self == DspIntSel::GpioInt0Irq2
190    }
191    #[doc = "GPIO_INT0_IRQ3"]
192    #[inline(always)]
193    pub fn is_gpio_int0_irq3(&self) -> bool {
194        *self == DspIntSel::GpioInt0Irq3
195    }
196    #[doc = "GPIO_INT0_IRQ4"]
197    #[inline(always)]
198    pub fn is_gpio_int0_irq4(&self) -> bool {
199        *self == DspIntSel::GpioInt0Irq4
200    }
201    #[doc = "GPIO_INT0_IRQ5"]
202    #[inline(always)]
203    pub fn is_gpio_int0_irq5(&self) -> bool {
204        *self == DspIntSel::GpioInt0Irq5
205    }
206    #[doc = "GPIO_INT0_IRQ6"]
207    #[inline(always)]
208    pub fn is_gpio_int0_irq6(&self) -> bool {
209        *self == DspIntSel::GpioInt0Irq6
210    }
211    #[doc = "GPIO_INT0_IRQ7"]
212    #[inline(always)]
213    pub fn is_gpio_int0_irq7(&self) -> bool {
214        *self == DspIntSel::GpioInt0Irq7
215    }
216    #[doc = "NSHSGPIO_INT0"]
217    #[inline(always)]
218    pub fn is_nshsgpio_int0(&self) -> bool {
219        *self == DspIntSel::NshsgpioInt0
220    }
221    #[doc = "NSHSGPIO_INT1"]
222    #[inline(always)]
223    pub fn is_nshsgpio_int1(&self) -> bool {
224        *self == DspIntSel::NshsgpioInt1
225    }
226    #[doc = "WDT1"]
227    #[inline(always)]
228    pub fn is_wdt1(&self) -> bool {
229        *self == DspIntSel::Wdt1
230    }
231    #[doc = "DMAC0"]
232    #[inline(always)]
233    pub fn is_dmac0(&self) -> bool {
234        *self == DspIntSel::Dmac0
235    }
236    #[doc = "DMAC1"]
237    #[inline(always)]
238    pub fn is_dmac1(&self) -> bool {
239        *self == DspIntSel::Dmac1
240    }
241    #[doc = "MU"]
242    #[inline(always)]
243    pub fn is_mu(&self) -> bool {
244        *self == DspIntSel::Mu
245    }
246    #[doc = "UTICK0"]
247    #[inline(always)]
248    pub fn is_utick0(&self) -> bool {
249        *self == DspIntSel::Utick0
250    }
251    #[doc = "MRT0"]
252    #[inline(always)]
253    pub fn is_mrt0(&self) -> bool {
254        *self == DspIntSel::Mrt0
255    }
256    #[doc = "OS_EVENT_TIMER or OS_EVENT_WAKEUP"]
257    #[inline(always)]
258    pub fn is_os_event_timer_or_os_event_wakeup(&self) -> bool {
259        *self == DspIntSel::OsEventTimerOrOsEventWakeup
260    }
261    #[doc = "CT32BIT0"]
262    #[inline(always)]
263    pub fn is_ct32bit0(&self) -> bool {
264        *self == DspIntSel::Ct32bit0
265    }
266    #[doc = "CT32BIT1"]
267    #[inline(always)]
268    pub fn is_ct32bit1(&self) -> bool {
269        *self == DspIntSel::Ct32bit1
270    }
271    #[doc = "CT32BIT2"]
272    #[inline(always)]
273    pub fn is_ct32bit2(&self) -> bool {
274        *self == DspIntSel::Ct32bit2
275    }
276    #[doc = "CT32BIT3"]
277    #[inline(always)]
278    pub fn is_ct32bit3(&self) -> bool {
279        *self == DspIntSel::Ct32bit3
280    }
281    #[doc = "CT32BIT4"]
282    #[inline(always)]
283    pub fn is_ct32bit4(&self) -> bool {
284        *self == DspIntSel::Ct32bit4
285    }
286    #[doc = "RTC_LITE0_ALARM or RTC_LITE0_WAKEUP"]
287    #[inline(always)]
288    pub fn is_rtc_lite0_alarm_or_rtc_lite0_wakeup(&self) -> bool {
289        *self == DspIntSel::RtcLite0AlarmOrRtcLite0Wakeup
290    }
291    #[doc = "I3C0"]
292    #[inline(always)]
293    pub fn is_i3c0(&self) -> bool {
294        *self == DspIntSel::I3c0
295    }
296    #[doc = "DMIC0"]
297    #[inline(always)]
298    pub fn is_dmic0(&self) -> bool {
299        *self == DspIntSel::Dmic0
300    }
301    #[doc = "HWVAD0"]
302    #[inline(always)]
303    pub fn is_hwvad0(&self) -> bool {
304        *self == DspIntSel::Hwvad0
305    }
306    #[doc = "FLEXSPI"]
307    #[inline(always)]
308    pub fn is_flexspi(&self) -> bool {
309        *self == DspIntSel::Flexspi
310    }
311}
312#[doc = "Field `DSP_INT_SEL` writer - DSP Input(n) Selection. 34:1 Selection for each. . ."]
313pub type DspIntSelW<'a, REG> = crate::FieldWriter<'a, REG, 6, DspIntSel>;
314impl<'a, REG> DspIntSelW<'a, REG>
315where
316    REG: crate::Writable + crate::RegisterSpec,
317    REG::Ux: From<u8>,
318{
319    #[doc = "FLEXCOMM0"]
320    #[inline(always)]
321    pub fn flexcomm0(self) -> &'a mut crate::W<REG> {
322        self.variant(DspIntSel::Flexcomm0)
323    }
324    #[doc = "FLEXCOMM1"]
325    #[inline(always)]
326    pub fn flexcomm1(self) -> &'a mut crate::W<REG> {
327        self.variant(DspIntSel::Flexcomm1)
328    }
329    #[doc = "FLEXCOMM2"]
330    #[inline(always)]
331    pub fn flexcomm2(self) -> &'a mut crate::W<REG> {
332        self.variant(DspIntSel::Flexcomm2)
333    }
334    #[doc = "FLEXCOMM3"]
335    #[inline(always)]
336    pub fn flexcomm3(self) -> &'a mut crate::W<REG> {
337        self.variant(DspIntSel::Flexcomm3)
338    }
339    #[doc = "FLEXCOMM4"]
340    #[inline(always)]
341    pub fn flexcomm4(self) -> &'a mut crate::W<REG> {
342        self.variant(DspIntSel::Flexcomm4)
343    }
344    #[doc = "FLEXCOMM5"]
345    #[inline(always)]
346    pub fn flexcomm5(self) -> &'a mut crate::W<REG> {
347        self.variant(DspIntSel::Flexcomm5)
348    }
349    #[doc = "FLEXCOMM6"]
350    #[inline(always)]
351    pub fn flexcomm6(self) -> &'a mut crate::W<REG> {
352        self.variant(DspIntSel::Flexcomm6)
353    }
354    #[doc = "FLEXCOMM7"]
355    #[inline(always)]
356    pub fn flexcomm7(self) -> &'a mut crate::W<REG> {
357        self.variant(DspIntSel::Flexcomm7)
358    }
359    #[doc = "GPIO_INT0_IRQ0"]
360    #[inline(always)]
361    pub fn gpio_int0_irq0(self) -> &'a mut crate::W<REG> {
362        self.variant(DspIntSel::GpioInt0Irq0)
363    }
364    #[doc = "GPIO_INT0_IRQ1"]
365    #[inline(always)]
366    pub fn gpio_int0_irq1(self) -> &'a mut crate::W<REG> {
367        self.variant(DspIntSel::GpioInt0Irq1)
368    }
369    #[doc = "GPIO_INT0_IRQ2"]
370    #[inline(always)]
371    pub fn gpio_int0_irq2(self) -> &'a mut crate::W<REG> {
372        self.variant(DspIntSel::GpioInt0Irq2)
373    }
374    #[doc = "GPIO_INT0_IRQ3"]
375    #[inline(always)]
376    pub fn gpio_int0_irq3(self) -> &'a mut crate::W<REG> {
377        self.variant(DspIntSel::GpioInt0Irq3)
378    }
379    #[doc = "GPIO_INT0_IRQ4"]
380    #[inline(always)]
381    pub fn gpio_int0_irq4(self) -> &'a mut crate::W<REG> {
382        self.variant(DspIntSel::GpioInt0Irq4)
383    }
384    #[doc = "GPIO_INT0_IRQ5"]
385    #[inline(always)]
386    pub fn gpio_int0_irq5(self) -> &'a mut crate::W<REG> {
387        self.variant(DspIntSel::GpioInt0Irq5)
388    }
389    #[doc = "GPIO_INT0_IRQ6"]
390    #[inline(always)]
391    pub fn gpio_int0_irq6(self) -> &'a mut crate::W<REG> {
392        self.variant(DspIntSel::GpioInt0Irq6)
393    }
394    #[doc = "GPIO_INT0_IRQ7"]
395    #[inline(always)]
396    pub fn gpio_int0_irq7(self) -> &'a mut crate::W<REG> {
397        self.variant(DspIntSel::GpioInt0Irq7)
398    }
399    #[doc = "NSHSGPIO_INT0"]
400    #[inline(always)]
401    pub fn nshsgpio_int0(self) -> &'a mut crate::W<REG> {
402        self.variant(DspIntSel::NshsgpioInt0)
403    }
404    #[doc = "NSHSGPIO_INT1"]
405    #[inline(always)]
406    pub fn nshsgpio_int1(self) -> &'a mut crate::W<REG> {
407        self.variant(DspIntSel::NshsgpioInt1)
408    }
409    #[doc = "WDT1"]
410    #[inline(always)]
411    pub fn wdt1(self) -> &'a mut crate::W<REG> {
412        self.variant(DspIntSel::Wdt1)
413    }
414    #[doc = "DMAC0"]
415    #[inline(always)]
416    pub fn dmac0(self) -> &'a mut crate::W<REG> {
417        self.variant(DspIntSel::Dmac0)
418    }
419    #[doc = "DMAC1"]
420    #[inline(always)]
421    pub fn dmac1(self) -> &'a mut crate::W<REG> {
422        self.variant(DspIntSel::Dmac1)
423    }
424    #[doc = "MU"]
425    #[inline(always)]
426    pub fn mu(self) -> &'a mut crate::W<REG> {
427        self.variant(DspIntSel::Mu)
428    }
429    #[doc = "UTICK0"]
430    #[inline(always)]
431    pub fn utick0(self) -> &'a mut crate::W<REG> {
432        self.variant(DspIntSel::Utick0)
433    }
434    #[doc = "MRT0"]
435    #[inline(always)]
436    pub fn mrt0(self) -> &'a mut crate::W<REG> {
437        self.variant(DspIntSel::Mrt0)
438    }
439    #[doc = "OS_EVENT_TIMER or OS_EVENT_WAKEUP"]
440    #[inline(always)]
441    pub fn os_event_timer_or_os_event_wakeup(self) -> &'a mut crate::W<REG> {
442        self.variant(DspIntSel::OsEventTimerOrOsEventWakeup)
443    }
444    #[doc = "CT32BIT0"]
445    #[inline(always)]
446    pub fn ct32bit0(self) -> &'a mut crate::W<REG> {
447        self.variant(DspIntSel::Ct32bit0)
448    }
449    #[doc = "CT32BIT1"]
450    #[inline(always)]
451    pub fn ct32bit1(self) -> &'a mut crate::W<REG> {
452        self.variant(DspIntSel::Ct32bit1)
453    }
454    #[doc = "CT32BIT2"]
455    #[inline(always)]
456    pub fn ct32bit2(self) -> &'a mut crate::W<REG> {
457        self.variant(DspIntSel::Ct32bit2)
458    }
459    #[doc = "CT32BIT3"]
460    #[inline(always)]
461    pub fn ct32bit3(self) -> &'a mut crate::W<REG> {
462        self.variant(DspIntSel::Ct32bit3)
463    }
464    #[doc = "CT32BIT4"]
465    #[inline(always)]
466    pub fn ct32bit4(self) -> &'a mut crate::W<REG> {
467        self.variant(DspIntSel::Ct32bit4)
468    }
469    #[doc = "RTC_LITE0_ALARM or RTC_LITE0_WAKEUP"]
470    #[inline(always)]
471    pub fn rtc_lite0_alarm_or_rtc_lite0_wakeup(self) -> &'a mut crate::W<REG> {
472        self.variant(DspIntSel::RtcLite0AlarmOrRtcLite0Wakeup)
473    }
474    #[doc = "I3C0"]
475    #[inline(always)]
476    pub fn i3c0(self) -> &'a mut crate::W<REG> {
477        self.variant(DspIntSel::I3c0)
478    }
479    #[doc = "DMIC0"]
480    #[inline(always)]
481    pub fn dmic0(self) -> &'a mut crate::W<REG> {
482        self.variant(DspIntSel::Dmic0)
483    }
484    #[doc = "HWVAD0"]
485    #[inline(always)]
486    pub fn hwvad0(self) -> &'a mut crate::W<REG> {
487        self.variant(DspIntSel::Hwvad0)
488    }
489    #[doc = "FLEXSPI"]
490    #[inline(always)]
491    pub fn flexspi(self) -> &'a mut crate::W<REG> {
492        self.variant(DspIntSel::Flexspi)
493    }
494}
495impl R {
496    #[doc = "Bits 0:5 - DSP Input(n) Selection. 34:1 Selection for each. . ."]
497    #[inline(always)]
498    pub fn dsp_int_sel(&self) -> DspIntSelR {
499        DspIntSelR::new((self.bits & 0x3f) as u8)
500    }
501}
502#[cfg(feature = "debug")]
503impl core::fmt::Debug for R {
504    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
505        f.debug_struct("DSP_INT_SEL")
506            .field("dsp_int_sel", &self.dsp_int_sel())
507            .finish()
508    }
509}
510impl W {
511    #[doc = "Bits 0:5 - DSP Input(n) Selection. 34:1 Selection for each. . ."]
512    #[inline(always)]
513    pub fn dsp_int_sel(&mut self) -> DspIntSelW<DspIntSelSpec> {
514        DspIntSelW::new(self, 0)
515    }
516}
517#[doc = "DSP Interrupt Input Multiplexers N\n\nYou can [`read`](crate::Reg::read) this register and get [`dsp_int_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dsp_int_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
518pub struct DspIntSelSpec;
519impl crate::RegisterSpec for DspIntSelSpec {
520    type Ux = u32;
521}
522#[doc = "`read()` method returns [`dsp_int_sel::R`](R) reader structure"]
523impl crate::Readable for DspIntSelSpec {}
524#[doc = "`write(|w| ..)` method takes [`dsp_int_sel::W`](W) writer structure"]
525impl crate::Writable for DspIntSelSpec {
526    type Safety = crate::Unsafe;
527    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
528    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
529}
530#[doc = "`reset()` method sets DSP_INT_SEL[%s]
531to value 0x3f"]
532impl crate::Resettable for DspIntSelSpec {
533    const RESET_VALUE: u32 = 0x3f;
534}
mimxrt685s_pac/inputmux/dsp_int_sel.rs

mimxrt685s_pac/inputmux/
dsp_int_sel.rs
