mimxrt685s_pac/inputmux/
dmac0_req_ena0_set.rs

1#[doc = "Register `DMAC0_REQ_ENA0_SET` writer"]
2pub type W = crate::W<Dmac0ReqEna0SetSpec>;
3#[doc = "FLEXCOMM0 RX enable set\n\nValue on reset: 0"]
4#[cfg_attr(feature = "defmt", derive(defmt::Format))]
5#[derive(Clone, Copy, Debug, PartialEq, Eq)]
6pub enum Flexcomm0Rx {
7    #[doc = "0: No Effect"]
8    NoEffect = 0,
9    #[doc = "1: Sets the ENA0 Bit"]
10    SetEna0Bit = 1,
11}
12impl From<Flexcomm0Rx> for bool {
13    #[inline(always)]
14    fn from(variant: Flexcomm0Rx) -> Self {
15        variant as u8 != 0
16    }
17}
18#[doc = "Field `FLEXCOMM0_RX` writer - FLEXCOMM0 RX enable set"]
19pub type Flexcomm0RxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm0Rx>;
20impl<'a, REG> Flexcomm0RxW<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    #[doc = "No Effect"]
25    #[inline(always)]
26    pub fn no_effect(self) -> &'a mut crate::W<REG> {
27        self.variant(Flexcomm0Rx::NoEffect)
28    }
29    #[doc = "Sets the ENA0 Bit"]
30    #[inline(always)]
31    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
32        self.variant(Flexcomm0Rx::SetEna0Bit)
33    }
34}
35#[doc = "FLEXCOMM0 TX enable set\n\nValue on reset: 0"]
36#[cfg_attr(feature = "defmt", derive(defmt::Format))]
37#[derive(Clone, Copy, Debug, PartialEq, Eq)]
38pub enum Flexcomm0Tx {
39    #[doc = "0: No Effect"]
40    NoEffect = 0,
41    #[doc = "1: Sets the ENA0 Bit"]
42    SetEna0Bit = 1,
43}
44impl From<Flexcomm0Tx> for bool {
45    #[inline(always)]
46    fn from(variant: Flexcomm0Tx) -> Self {
47        variant as u8 != 0
48    }
49}
50#[doc = "Field `FLEXCOMM0_TX` writer - FLEXCOMM0 TX enable set"]
51pub type Flexcomm0TxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm0Tx>;
52impl<'a, REG> Flexcomm0TxW<'a, REG>
53where
54    REG: crate::Writable + crate::RegisterSpec,
55{
56    #[doc = "No Effect"]
57    #[inline(always)]
58    pub fn no_effect(self) -> &'a mut crate::W<REG> {
59        self.variant(Flexcomm0Tx::NoEffect)
60    }
61    #[doc = "Sets the ENA0 Bit"]
62    #[inline(always)]
63    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
64        self.variant(Flexcomm0Tx::SetEna0Bit)
65    }
66}
67#[doc = "FLEXCOMM1 RX enable set\n\nValue on reset: 0"]
68#[cfg_attr(feature = "defmt", derive(defmt::Format))]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum Flexcomm1Rx {
71    #[doc = "0: No Effect"]
72    NoEffect = 0,
73    #[doc = "1: Sets the ENA0 Bit"]
74    SetEna0Bit = 1,
75}
76impl From<Flexcomm1Rx> for bool {
77    #[inline(always)]
78    fn from(variant: Flexcomm1Rx) -> Self {
79        variant as u8 != 0
80    }
81}
82#[doc = "Field `FLEXCOMM1_RX` writer - FLEXCOMM1 RX enable set"]
83pub type Flexcomm1RxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm1Rx>;
84impl<'a, REG> Flexcomm1RxW<'a, REG>
85where
86    REG: crate::Writable + crate::RegisterSpec,
87{
88    #[doc = "No Effect"]
89    #[inline(always)]
90    pub fn no_effect(self) -> &'a mut crate::W<REG> {
91        self.variant(Flexcomm1Rx::NoEffect)
92    }
93    #[doc = "Sets the ENA0 Bit"]
94    #[inline(always)]
95    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
96        self.variant(Flexcomm1Rx::SetEna0Bit)
97    }
98}
99#[doc = "FLEXCOMM1 TX enable set\n\nValue on reset: 0"]
100#[cfg_attr(feature = "defmt", derive(defmt::Format))]
101#[derive(Clone, Copy, Debug, PartialEq, Eq)]
102pub enum Flexcomm1Tx {
103    #[doc = "0: No Effect"]
104    NoEffect = 0,
105    #[doc = "1: Sets the ENA0 Bit"]
106    SetEna0Bit = 1,
107}
108impl From<Flexcomm1Tx> for bool {
109    #[inline(always)]
110    fn from(variant: Flexcomm1Tx) -> Self {
111        variant as u8 != 0
112    }
113}
114#[doc = "Field `FLEXCOMM1_TX` writer - FLEXCOMM1 TX enable set"]
115pub type Flexcomm1TxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm1Tx>;
116impl<'a, REG> Flexcomm1TxW<'a, REG>
117where
118    REG: crate::Writable + crate::RegisterSpec,
119{
120    #[doc = "No Effect"]
121    #[inline(always)]
122    pub fn no_effect(self) -> &'a mut crate::W<REG> {
123        self.variant(Flexcomm1Tx::NoEffect)
124    }
125    #[doc = "Sets the ENA0 Bit"]
126    #[inline(always)]
127    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
128        self.variant(Flexcomm1Tx::SetEna0Bit)
129    }
130}
131#[doc = "FLEXCOMM2 RX enable set\n\nValue on reset: 0"]
132#[cfg_attr(feature = "defmt", derive(defmt::Format))]
133#[derive(Clone, Copy, Debug, PartialEq, Eq)]
134pub enum Flexcomm2Rx {
135    #[doc = "0: No Effect"]
136    NoEffect = 0,
137    #[doc = "1: Sets the ENA0 Bit"]
138    SetEna0Bit = 1,
139}
140impl From<Flexcomm2Rx> for bool {
141    #[inline(always)]
142    fn from(variant: Flexcomm2Rx) -> Self {
143        variant as u8 != 0
144    }
145}
146#[doc = "Field `FLEXCOMM2_RX` writer - FLEXCOMM2 RX enable set"]
147pub type Flexcomm2RxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm2Rx>;
148impl<'a, REG> Flexcomm2RxW<'a, REG>
149where
150    REG: crate::Writable + crate::RegisterSpec,
151{
152    #[doc = "No Effect"]
153    #[inline(always)]
154    pub fn no_effect(self) -> &'a mut crate::W<REG> {
155        self.variant(Flexcomm2Rx::NoEffect)
156    }
157    #[doc = "Sets the ENA0 Bit"]
158    #[inline(always)]
159    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
160        self.variant(Flexcomm2Rx::SetEna0Bit)
161    }
162}
163#[doc = "FLEXCOMM2 TX enable set\n\nValue on reset: 0"]
164#[cfg_attr(feature = "defmt", derive(defmt::Format))]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum Flexcomm2Tx {
167    #[doc = "0: No Effect"]
168    NoEffect = 0,
169    #[doc = "1: Sets the ENA0 Bit"]
170    SetEna0Bit = 1,
171}
172impl From<Flexcomm2Tx> for bool {
173    #[inline(always)]
174    fn from(variant: Flexcomm2Tx) -> Self {
175        variant as u8 != 0
176    }
177}
178#[doc = "Field `FLEXCOMM2_TX` writer - FLEXCOMM2 TX enable set"]
179pub type Flexcomm2TxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm2Tx>;
180impl<'a, REG> Flexcomm2TxW<'a, REG>
181where
182    REG: crate::Writable + crate::RegisterSpec,
183{
184    #[doc = "No Effect"]
185    #[inline(always)]
186    pub fn no_effect(self) -> &'a mut crate::W<REG> {
187        self.variant(Flexcomm2Tx::NoEffect)
188    }
189    #[doc = "Sets the ENA0 Bit"]
190    #[inline(always)]
191    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
192        self.variant(Flexcomm2Tx::SetEna0Bit)
193    }
194}
195#[doc = "FLEXCOMM3 RX enable set\n\nValue on reset: 0"]
196#[cfg_attr(feature = "defmt", derive(defmt::Format))]
197#[derive(Clone, Copy, Debug, PartialEq, Eq)]
198pub enum Flexcomm3Rx {
199    #[doc = "0: No Effect"]
200    NoEffect = 0,
201    #[doc = "1: Sets the ENA0 Bit"]
202    SetEna0Bit = 1,
203}
204impl From<Flexcomm3Rx> for bool {
205    #[inline(always)]
206    fn from(variant: Flexcomm3Rx) -> Self {
207        variant as u8 != 0
208    }
209}
210#[doc = "Field `FLEXCOMM3_RX` writer - FLEXCOMM3 RX enable set"]
211pub type Flexcomm3RxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm3Rx>;
212impl<'a, REG> Flexcomm3RxW<'a, REG>
213where
214    REG: crate::Writable + crate::RegisterSpec,
215{
216    #[doc = "No Effect"]
217    #[inline(always)]
218    pub fn no_effect(self) -> &'a mut crate::W<REG> {
219        self.variant(Flexcomm3Rx::NoEffect)
220    }
221    #[doc = "Sets the ENA0 Bit"]
222    #[inline(always)]
223    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
224        self.variant(Flexcomm3Rx::SetEna0Bit)
225    }
226}
227#[doc = "FLEXCOMM3 TX enable set\n\nValue on reset: 0"]
228#[cfg_attr(feature = "defmt", derive(defmt::Format))]
229#[derive(Clone, Copy, Debug, PartialEq, Eq)]
230pub enum Flexcomm3Tx {
231    #[doc = "0: No Effect"]
232    NoEffect = 0,
233    #[doc = "1: Sets the ENA0 Bit"]
234    SetEna0Bit = 1,
235}
236impl From<Flexcomm3Tx> for bool {
237    #[inline(always)]
238    fn from(variant: Flexcomm3Tx) -> Self {
239        variant as u8 != 0
240    }
241}
242#[doc = "Field `FLEXCOMM3_TX` writer - FLEXCOMM3 TX enable set"]
243pub type Flexcomm3TxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm3Tx>;
244impl<'a, REG> Flexcomm3TxW<'a, REG>
245where
246    REG: crate::Writable + crate::RegisterSpec,
247{
248    #[doc = "No Effect"]
249    #[inline(always)]
250    pub fn no_effect(self) -> &'a mut crate::W<REG> {
251        self.variant(Flexcomm3Tx::NoEffect)
252    }
253    #[doc = "Sets the ENA0 Bit"]
254    #[inline(always)]
255    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
256        self.variant(Flexcomm3Tx::SetEna0Bit)
257    }
258}
259#[doc = "FLEXCOMM4 RX enable set\n\nValue on reset: 0"]
260#[cfg_attr(feature = "defmt", derive(defmt::Format))]
261#[derive(Clone, Copy, Debug, PartialEq, Eq)]
262pub enum Flexcomm4Rx {
263    #[doc = "0: No Effect"]
264    NoEffect = 0,
265    #[doc = "1: Sets the ENA0 Bit"]
266    SetEna0Bit = 1,
267}
268impl From<Flexcomm4Rx> for bool {
269    #[inline(always)]
270    fn from(variant: Flexcomm4Rx) -> Self {
271        variant as u8 != 0
272    }
273}
274#[doc = "Field `FLEXCOMM4_RX` writer - FLEXCOMM4 RX enable set"]
275pub type Flexcomm4RxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm4Rx>;
276impl<'a, REG> Flexcomm4RxW<'a, REG>
277where
278    REG: crate::Writable + crate::RegisterSpec,
279{
280    #[doc = "No Effect"]
281    #[inline(always)]
282    pub fn no_effect(self) -> &'a mut crate::W<REG> {
283        self.variant(Flexcomm4Rx::NoEffect)
284    }
285    #[doc = "Sets the ENA0 Bit"]
286    #[inline(always)]
287    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
288        self.variant(Flexcomm4Rx::SetEna0Bit)
289    }
290}
291#[doc = "FLEXCOMM4 TX enable set\n\nValue on reset: 0"]
292#[cfg_attr(feature = "defmt", derive(defmt::Format))]
293#[derive(Clone, Copy, Debug, PartialEq, Eq)]
294pub enum Flexcomm4Tx {
295    #[doc = "0: No Effect"]
296    NoEffect = 0,
297    #[doc = "1: Sets the ENA0 Bit"]
298    SetEna0Bit = 1,
299}
300impl From<Flexcomm4Tx> for bool {
301    #[inline(always)]
302    fn from(variant: Flexcomm4Tx) -> Self {
303        variant as u8 != 0
304    }
305}
306#[doc = "Field `FLEXCOMM4_TX` writer - FLEXCOMM4 TX enable set"]
307pub type Flexcomm4TxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm4Tx>;
308impl<'a, REG> Flexcomm4TxW<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "No Effect"]
313    #[inline(always)]
314    pub fn no_effect(self) -> &'a mut crate::W<REG> {
315        self.variant(Flexcomm4Tx::NoEffect)
316    }
317    #[doc = "Sets the ENA0 Bit"]
318    #[inline(always)]
319    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
320        self.variant(Flexcomm4Tx::SetEna0Bit)
321    }
322}
323#[doc = "FLEXCOMM5 RX enable set\n\nValue on reset: 0"]
324#[cfg_attr(feature = "defmt", derive(defmt::Format))]
325#[derive(Clone, Copy, Debug, PartialEq, Eq)]
326pub enum Flexcomm5Rx {
327    #[doc = "0: No Effect"]
328    NoEffect = 0,
329    #[doc = "1: Sets the ENA0 Bit"]
330    SetEna0Bit = 1,
331}
332impl From<Flexcomm5Rx> for bool {
333    #[inline(always)]
334    fn from(variant: Flexcomm5Rx) -> Self {
335        variant as u8 != 0
336    }
337}
338#[doc = "Field `FLEXCOMM5_RX` writer - FLEXCOMM5 RX enable set"]
339pub type Flexcomm5RxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm5Rx>;
340impl<'a, REG> Flexcomm5RxW<'a, REG>
341where
342    REG: crate::Writable + crate::RegisterSpec,
343{
344    #[doc = "No Effect"]
345    #[inline(always)]
346    pub fn no_effect(self) -> &'a mut crate::W<REG> {
347        self.variant(Flexcomm5Rx::NoEffect)
348    }
349    #[doc = "Sets the ENA0 Bit"]
350    #[inline(always)]
351    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
352        self.variant(Flexcomm5Rx::SetEna0Bit)
353    }
354}
355#[doc = "FLEXCOMM5 TX enable set\n\nValue on reset: 0"]
356#[cfg_attr(feature = "defmt", derive(defmt::Format))]
357#[derive(Clone, Copy, Debug, PartialEq, Eq)]
358pub enum Flexcomm5Tx {
359    #[doc = "0: No Effect"]
360    NoEffect = 0,
361    #[doc = "1: Sets the ENA0 Bit"]
362    SetEna0Bit = 1,
363}
364impl From<Flexcomm5Tx> for bool {
365    #[inline(always)]
366    fn from(variant: Flexcomm5Tx) -> Self {
367        variant as u8 != 0
368    }
369}
370#[doc = "Field `FLEXCOMM5_TX` writer - FLEXCOMM5 TX enable set"]
371pub type Flexcomm5TxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm5Tx>;
372impl<'a, REG> Flexcomm5TxW<'a, REG>
373where
374    REG: crate::Writable + crate::RegisterSpec,
375{
376    #[doc = "No Effect"]
377    #[inline(always)]
378    pub fn no_effect(self) -> &'a mut crate::W<REG> {
379        self.variant(Flexcomm5Tx::NoEffect)
380    }
381    #[doc = "Sets the ENA0 Bit"]
382    #[inline(always)]
383    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
384        self.variant(Flexcomm5Tx::SetEna0Bit)
385    }
386}
387#[doc = "FLEXCOMM6 RX enable set\n\nValue on reset: 0"]
388#[cfg_attr(feature = "defmt", derive(defmt::Format))]
389#[derive(Clone, Copy, Debug, PartialEq, Eq)]
390pub enum Flexcomm6Rx {
391    #[doc = "0: No Effect"]
392    NoEffect = 0,
393    #[doc = "1: Sets the ENA0 Bit"]
394    SetEna0Bit = 1,
395}
396impl From<Flexcomm6Rx> for bool {
397    #[inline(always)]
398    fn from(variant: Flexcomm6Rx) -> Self {
399        variant as u8 != 0
400    }
401}
402#[doc = "Field `FLEXCOMM6_RX` writer - FLEXCOMM6 RX enable set"]
403pub type Flexcomm6RxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm6Rx>;
404impl<'a, REG> Flexcomm6RxW<'a, REG>
405where
406    REG: crate::Writable + crate::RegisterSpec,
407{
408    #[doc = "No Effect"]
409    #[inline(always)]
410    pub fn no_effect(self) -> &'a mut crate::W<REG> {
411        self.variant(Flexcomm6Rx::NoEffect)
412    }
413    #[doc = "Sets the ENA0 Bit"]
414    #[inline(always)]
415    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
416        self.variant(Flexcomm6Rx::SetEna0Bit)
417    }
418}
419#[doc = "FLEXCOMM6 TX enable set\n\nValue on reset: 0"]
420#[cfg_attr(feature = "defmt", derive(defmt::Format))]
421#[derive(Clone, Copy, Debug, PartialEq, Eq)]
422pub enum Flexcomm6Tx {
423    #[doc = "0: No Effect"]
424    NoEffect = 0,
425    #[doc = "1: Sets the ENA0 Bit"]
426    SetEna0Bit = 1,
427}
428impl From<Flexcomm6Tx> for bool {
429    #[inline(always)]
430    fn from(variant: Flexcomm6Tx) -> Self {
431        variant as u8 != 0
432    }
433}
434#[doc = "Field `FLEXCOMM6_TX` writer - FLEXCOMM6 TX enable set"]
435pub type Flexcomm6TxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm6Tx>;
436impl<'a, REG> Flexcomm6TxW<'a, REG>
437where
438    REG: crate::Writable + crate::RegisterSpec,
439{
440    #[doc = "No Effect"]
441    #[inline(always)]
442    pub fn no_effect(self) -> &'a mut crate::W<REG> {
443        self.variant(Flexcomm6Tx::NoEffect)
444    }
445    #[doc = "Sets the ENA0 Bit"]
446    #[inline(always)]
447    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
448        self.variant(Flexcomm6Tx::SetEna0Bit)
449    }
450}
451#[doc = "FLEXCOMM7 RX enable set\n\nValue on reset: 0"]
452#[cfg_attr(feature = "defmt", derive(defmt::Format))]
453#[derive(Clone, Copy, Debug, PartialEq, Eq)]
454pub enum Flexcomm7Rx {
455    #[doc = "0: No Effect"]
456    NoEffect = 0,
457    #[doc = "1: Sets the ENA0 Bit"]
458    SetEna0Bit = 1,
459}
460impl From<Flexcomm7Rx> for bool {
461    #[inline(always)]
462    fn from(variant: Flexcomm7Rx) -> Self {
463        variant as u8 != 0
464    }
465}
466#[doc = "Field `FLEXCOMM7_RX` writer - FLEXCOMM7 RX enable set"]
467pub type Flexcomm7RxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm7Rx>;
468impl<'a, REG> Flexcomm7RxW<'a, REG>
469where
470    REG: crate::Writable + crate::RegisterSpec,
471{
472    #[doc = "No Effect"]
473    #[inline(always)]
474    pub fn no_effect(self) -> &'a mut crate::W<REG> {
475        self.variant(Flexcomm7Rx::NoEffect)
476    }
477    #[doc = "Sets the ENA0 Bit"]
478    #[inline(always)]
479    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
480        self.variant(Flexcomm7Rx::SetEna0Bit)
481    }
482}
483#[doc = "FLEXCOMM7 TX enable set\n\nValue on reset: 0"]
484#[cfg_attr(feature = "defmt", derive(defmt::Format))]
485#[derive(Clone, Copy, Debug, PartialEq, Eq)]
486pub enum Flexcomm7Tx {
487    #[doc = "0: No Effect"]
488    NoEffect = 0,
489    #[doc = "1: Sets the ENA0 Bit"]
490    SetEna0Bit = 1,
491}
492impl From<Flexcomm7Tx> for bool {
493    #[inline(always)]
494    fn from(variant: Flexcomm7Tx) -> Self {
495        variant as u8 != 0
496    }
497}
498#[doc = "Field `FLEXCOMM7_TX` writer - FLEXCOMM7 TX enable set"]
499pub type Flexcomm7TxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm7Tx>;
500impl<'a, REG> Flexcomm7TxW<'a, REG>
501where
502    REG: crate::Writable + crate::RegisterSpec,
503{
504    #[doc = "No Effect"]
505    #[inline(always)]
506    pub fn no_effect(self) -> &'a mut crate::W<REG> {
507        self.variant(Flexcomm7Tx::NoEffect)
508    }
509    #[doc = "Sets the ENA0 Bit"]
510    #[inline(always)]
511    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
512        self.variant(Flexcomm7Tx::SetEna0Bit)
513    }
514}
515#[doc = "DMIC0 channel 0 enable set\n\nValue on reset: 0"]
516#[cfg_attr(feature = "defmt", derive(defmt::Format))]
517#[derive(Clone, Copy, Debug, PartialEq, Eq)]
518pub enum Dmic0ch0 {
519    #[doc = "0: No Effect"]
520    NoEffect = 0,
521    #[doc = "1: Sets the ENA0 Bit"]
522    SetEna0Bit = 1,
523}
524impl From<Dmic0ch0> for bool {
525    #[inline(always)]
526    fn from(variant: Dmic0ch0) -> Self {
527        variant as u8 != 0
528    }
529}
530#[doc = "Field `DMIC0CH0` writer - DMIC0 channel 0 enable set"]
531pub type Dmic0ch0W<'a, REG> = crate::BitWriter<'a, REG, Dmic0ch0>;
532impl<'a, REG> Dmic0ch0W<'a, REG>
533where
534    REG: crate::Writable + crate::RegisterSpec,
535{
536    #[doc = "No Effect"]
537    #[inline(always)]
538    pub fn no_effect(self) -> &'a mut crate::W<REG> {
539        self.variant(Dmic0ch0::NoEffect)
540    }
541    #[doc = "Sets the ENA0 Bit"]
542    #[inline(always)]
543    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
544        self.variant(Dmic0ch0::SetEna0Bit)
545    }
546}
547#[doc = "DMIC0 channel 1 enable set\n\nValue on reset: 0"]
548#[cfg_attr(feature = "defmt", derive(defmt::Format))]
549#[derive(Clone, Copy, Debug, PartialEq, Eq)]
550pub enum Dmic0ch1 {
551    #[doc = "0: No Effect"]
552    NoEffect = 0,
553    #[doc = "1: Sets the ENA0 Bit"]
554    SetEna0Bit = 1,
555}
556impl From<Dmic0ch1> for bool {
557    #[inline(always)]
558    fn from(variant: Dmic0ch1) -> Self {
559        variant as u8 != 0
560    }
561}
562#[doc = "Field `DMIC0CH1` writer - DMIC0 channel 1 enable set"]
563pub type Dmic0ch1W<'a, REG> = crate::BitWriter<'a, REG, Dmic0ch1>;
564impl<'a, REG> Dmic0ch1W<'a, REG>
565where
566    REG: crate::Writable + crate::RegisterSpec,
567{
568    #[doc = "No Effect"]
569    #[inline(always)]
570    pub fn no_effect(self) -> &'a mut crate::W<REG> {
571        self.variant(Dmic0ch1::NoEffect)
572    }
573    #[doc = "Sets the ENA0 Bit"]
574    #[inline(always)]
575    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
576        self.variant(Dmic0ch1::SetEna0Bit)
577    }
578}
579#[doc = "DMIC0 channel 2 enable set\n\nValue on reset: 0"]
580#[cfg_attr(feature = "defmt", derive(defmt::Format))]
581#[derive(Clone, Copy, Debug, PartialEq, Eq)]
582pub enum Dmic0ch2 {
583    #[doc = "0: No Effect"]
584    NoEffect = 0,
585    #[doc = "1: Sets the ENA0 Bit"]
586    SetEna0Bit = 1,
587}
588impl From<Dmic0ch2> for bool {
589    #[inline(always)]
590    fn from(variant: Dmic0ch2) -> Self {
591        variant as u8 != 0
592    }
593}
594#[doc = "Field `DMIC0CH2` writer - DMIC0 channel 2 enable set"]
595pub type Dmic0ch2W<'a, REG> = crate::BitWriter<'a, REG, Dmic0ch2>;
596impl<'a, REG> Dmic0ch2W<'a, REG>
597where
598    REG: crate::Writable + crate::RegisterSpec,
599{
600    #[doc = "No Effect"]
601    #[inline(always)]
602    pub fn no_effect(self) -> &'a mut crate::W<REG> {
603        self.variant(Dmic0ch2::NoEffect)
604    }
605    #[doc = "Sets the ENA0 Bit"]
606    #[inline(always)]
607    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
608        self.variant(Dmic0ch2::SetEna0Bit)
609    }
610}
611#[doc = "DMIC0 channel 3 enable set\n\nValue on reset: 0"]
612#[cfg_attr(feature = "defmt", derive(defmt::Format))]
613#[derive(Clone, Copy, Debug, PartialEq, Eq)]
614pub enum Dmic0ch3 {
615    #[doc = "0: No Effect"]
616    NoEffect = 0,
617    #[doc = "1: Sets the ENA0 Bit"]
618    SetEna0Bit = 1,
619}
620impl From<Dmic0ch3> for bool {
621    #[inline(always)]
622    fn from(variant: Dmic0ch3) -> Self {
623        variant as u8 != 0
624    }
625}
626#[doc = "Field `DMIC0CH3` writer - DMIC0 channel 3 enable set"]
627pub type Dmic0ch3W<'a, REG> = crate::BitWriter<'a, REG, Dmic0ch3>;
628impl<'a, REG> Dmic0ch3W<'a, REG>
629where
630    REG: crate::Writable + crate::RegisterSpec,
631{
632    #[doc = "No Effect"]
633    #[inline(always)]
634    pub fn no_effect(self) -> &'a mut crate::W<REG> {
635        self.variant(Dmic0ch3::NoEffect)
636    }
637    #[doc = "Sets the ENA0 Bit"]
638    #[inline(always)]
639    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
640        self.variant(Dmic0ch3::SetEna0Bit)
641    }
642}
643#[doc = "DMIC0 channel 4 enable set\n\nValue on reset: 0"]
644#[cfg_attr(feature = "defmt", derive(defmt::Format))]
645#[derive(Clone, Copy, Debug, PartialEq, Eq)]
646pub enum Dmic0ch4 {
647    #[doc = "0: No Effect"]
648    NoEffect = 0,
649    #[doc = "1: Sets the ENA0 Bit"]
650    SetEna0Bit = 1,
651}
652impl From<Dmic0ch4> for bool {
653    #[inline(always)]
654    fn from(variant: Dmic0ch4) -> Self {
655        variant as u8 != 0
656    }
657}
658#[doc = "Field `DMIC0CH4` writer - DMIC0 channel 4 enable set"]
659pub type Dmic0ch4W<'a, REG> = crate::BitWriter<'a, REG, Dmic0ch4>;
660impl<'a, REG> Dmic0ch4W<'a, REG>
661where
662    REG: crate::Writable + crate::RegisterSpec,
663{
664    #[doc = "No Effect"]
665    #[inline(always)]
666    pub fn no_effect(self) -> &'a mut crate::W<REG> {
667        self.variant(Dmic0ch4::NoEffect)
668    }
669    #[doc = "Sets the ENA0 Bit"]
670    #[inline(always)]
671    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
672        self.variant(Dmic0ch4::SetEna0Bit)
673    }
674}
675#[doc = "DMIC0 channel 5 enable set\n\nValue on reset: 0"]
676#[cfg_attr(feature = "defmt", derive(defmt::Format))]
677#[derive(Clone, Copy, Debug, PartialEq, Eq)]
678pub enum Dmic0ch5 {
679    #[doc = "0: No Effect"]
680    NoEffect = 0,
681    #[doc = "1: Sets the ENA0 Bit"]
682    SetEna0Bit = 1,
683}
684impl From<Dmic0ch5> for bool {
685    #[inline(always)]
686    fn from(variant: Dmic0ch5) -> Self {
687        variant as u8 != 0
688    }
689}
690#[doc = "Field `DMIC0CH5` writer - DMIC0 channel 5 enable set"]
691pub type Dmic0ch5W<'a, REG> = crate::BitWriter<'a, REG, Dmic0ch5>;
692impl<'a, REG> Dmic0ch5W<'a, REG>
693where
694    REG: crate::Writable + crate::RegisterSpec,
695{
696    #[doc = "No Effect"]
697    #[inline(always)]
698    pub fn no_effect(self) -> &'a mut crate::W<REG> {
699        self.variant(Dmic0ch5::NoEffect)
700    }
701    #[doc = "Sets the ENA0 Bit"]
702    #[inline(always)]
703    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
704        self.variant(Dmic0ch5::SetEna0Bit)
705    }
706}
707#[doc = "DMIC0 channel 6 enable set\n\nValue on reset: 0"]
708#[cfg_attr(feature = "defmt", derive(defmt::Format))]
709#[derive(Clone, Copy, Debug, PartialEq, Eq)]
710pub enum Dmic0ch6 {
711    #[doc = "0: No Effect"]
712    NoEffect = 0,
713    #[doc = "1: Sets the ENA0 Bit"]
714    SetEna0Bit = 1,
715}
716impl From<Dmic0ch6> for bool {
717    #[inline(always)]
718    fn from(variant: Dmic0ch6) -> Self {
719        variant as u8 != 0
720    }
721}
722#[doc = "Field `DMIC0CH6` writer - DMIC0 channel 6 enable set"]
723pub type Dmic0ch6W<'a, REG> = crate::BitWriter<'a, REG, Dmic0ch6>;
724impl<'a, REG> Dmic0ch6W<'a, REG>
725where
726    REG: crate::Writable + crate::RegisterSpec,
727{
728    #[doc = "No Effect"]
729    #[inline(always)]
730    pub fn no_effect(self) -> &'a mut crate::W<REG> {
731        self.variant(Dmic0ch6::NoEffect)
732    }
733    #[doc = "Sets the ENA0 Bit"]
734    #[inline(always)]
735    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
736        self.variant(Dmic0ch6::SetEna0Bit)
737    }
738}
739#[doc = "DMIC0 channel 7 enable set\n\nValue on reset: 0"]
740#[cfg_attr(feature = "defmt", derive(defmt::Format))]
741#[derive(Clone, Copy, Debug, PartialEq, Eq)]
742pub enum Dmic0ch7 {
743    #[doc = "0: No Effect"]
744    NoEffect = 0,
745    #[doc = "1: Sets the ENA0 Bit"]
746    SetEna0Bit = 1,
747}
748impl From<Dmic0ch7> for bool {
749    #[inline(always)]
750    fn from(variant: Dmic0ch7) -> Self {
751        variant as u8 != 0
752    }
753}
754#[doc = "Field `DMIC0CH7` writer - DMIC0 channel 7 enable set"]
755pub type Dmic0ch7W<'a, REG> = crate::BitWriter<'a, REG, Dmic0ch7>;
756impl<'a, REG> Dmic0ch7W<'a, REG>
757where
758    REG: crate::Writable + crate::RegisterSpec,
759{
760    #[doc = "No Effect"]
761    #[inline(always)]
762    pub fn no_effect(self) -> &'a mut crate::W<REG> {
763        self.variant(Dmic0ch7::NoEffect)
764    }
765    #[doc = "Sets the ENA0 Bit"]
766    #[inline(always)]
767    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
768        self.variant(Dmic0ch7::SetEna0Bit)
769    }
770}
771#[doc = "I3C RX enable set\n\nValue on reset: 0"]
772#[cfg_attr(feature = "defmt", derive(defmt::Format))]
773#[derive(Clone, Copy, Debug, PartialEq, Eq)]
774pub enum I3c0Rx {
775    #[doc = "0: No Effect"]
776    NoEffect = 0,
777    #[doc = "1: Sets the ENA0 Bit"]
778    SetEna0Bit = 1,
779}
780impl From<I3c0Rx> for bool {
781    #[inline(always)]
782    fn from(variant: I3c0Rx) -> Self {
783        variant as u8 != 0
784    }
785}
786#[doc = "Field `I3C0_RX` writer - I3C RX enable set"]
787pub type I3c0RxW<'a, REG> = crate::BitWriter<'a, REG, I3c0Rx>;
788impl<'a, REG> I3c0RxW<'a, REG>
789where
790    REG: crate::Writable + crate::RegisterSpec,
791{
792    #[doc = "No Effect"]
793    #[inline(always)]
794    pub fn no_effect(self) -> &'a mut crate::W<REG> {
795        self.variant(I3c0Rx::NoEffect)
796    }
797    #[doc = "Sets the ENA0 Bit"]
798    #[inline(always)]
799    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
800        self.variant(I3c0Rx::SetEna0Bit)
801    }
802}
803#[doc = "I3C TX enable set\n\nValue on reset: 0"]
804#[cfg_attr(feature = "defmt", derive(defmt::Format))]
805#[derive(Clone, Copy, Debug, PartialEq, Eq)]
806pub enum I3c0Tx {
807    #[doc = "0: No Effect"]
808    NoEffect = 0,
809    #[doc = "1: Sets the ENA0 Bit"]
810    SetEna0Bit = 1,
811}
812impl From<I3c0Tx> for bool {
813    #[inline(always)]
814    fn from(variant: I3c0Tx) -> Self {
815        variant as u8 != 0
816    }
817}
818#[doc = "Field `I3C0_TX` writer - I3C TX enable set"]
819pub type I3c0TxW<'a, REG> = crate::BitWriter<'a, REG, I3c0Tx>;
820impl<'a, REG> I3c0TxW<'a, REG>
821where
822    REG: crate::Writable + crate::RegisterSpec,
823{
824    #[doc = "No Effect"]
825    #[inline(always)]
826    pub fn no_effect(self) -> &'a mut crate::W<REG> {
827        self.variant(I3c0Tx::NoEffect)
828    }
829    #[doc = "Sets the ENA0 Bit"]
830    #[inline(always)]
831    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
832        self.variant(I3c0Tx::SetEna0Bit)
833    }
834}
835#[doc = "FLEXCOMM14 TX enable set\n\nValue on reset: 0"]
836#[cfg_attr(feature = "defmt", derive(defmt::Format))]
837#[derive(Clone, Copy, Debug, PartialEq, Eq)]
838pub enum Flexcomm14Rx {
839    #[doc = "0: No Effect"]
840    NoEffect = 0,
841    #[doc = "1: Sets the ENA0 Bit"]
842    SetEna0Bit = 1,
843}
844impl From<Flexcomm14Rx> for bool {
845    #[inline(always)]
846    fn from(variant: Flexcomm14Rx) -> Self {
847        variant as u8 != 0
848    }
849}
850#[doc = "Field `FLEXCOMM14_RX` writer - FLEXCOMM14 TX enable set"]
851pub type Flexcomm14RxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm14Rx>;
852impl<'a, REG> Flexcomm14RxW<'a, REG>
853where
854    REG: crate::Writable + crate::RegisterSpec,
855{
856    #[doc = "No Effect"]
857    #[inline(always)]
858    pub fn no_effect(self) -> &'a mut crate::W<REG> {
859        self.variant(Flexcomm14Rx::NoEffect)
860    }
861    #[doc = "Sets the ENA0 Bit"]
862    #[inline(always)]
863    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
864        self.variant(Flexcomm14Rx::SetEna0Bit)
865    }
866}
867#[doc = "FLEXCOMM15 RX enable set\n\nValue on reset: 0"]
868#[cfg_attr(feature = "defmt", derive(defmt::Format))]
869#[derive(Clone, Copy, Debug, PartialEq, Eq)]
870pub enum Flexcomm14Tx {
871    #[doc = "0: No Effect"]
872    NoEffect = 0,
873    #[doc = "1: Sets the ENA0 Bit"]
874    SetEna0Bit = 1,
875}
876impl From<Flexcomm14Tx> for bool {
877    #[inline(always)]
878    fn from(variant: Flexcomm14Tx) -> Self {
879        variant as u8 != 0
880    }
881}
882#[doc = "Field `FLEXCOMM14_TX` writer - FLEXCOMM15 RX enable set"]
883pub type Flexcomm14TxW<'a, REG> = crate::BitWriter<'a, REG, Flexcomm14Tx>;
884impl<'a, REG> Flexcomm14TxW<'a, REG>
885where
886    REG: crate::Writable + crate::RegisterSpec,
887{
888    #[doc = "No Effect"]
889    #[inline(always)]
890    pub fn no_effect(self) -> &'a mut crate::W<REG> {
891        self.variant(Flexcomm14Tx::NoEffect)
892    }
893    #[doc = "Sets the ENA0 Bit"]
894    #[inline(always)]
895    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
896        self.variant(Flexcomm14Tx::SetEna0Bit)
897    }
898}
899#[doc = "Hash enable set\n\nValue on reset: 0"]
900#[cfg_attr(feature = "defmt", derive(defmt::Format))]
901#[derive(Clone, Copy, Debug, PartialEq, Eq)]
902pub enum Hashcrypt {
903    #[doc = "0: No Effect"]
904    NoEffect = 0,
905    #[doc = "1: Sets the ENA0 Bit"]
906    SetEna0Bit = 1,
907}
908impl From<Hashcrypt> for bool {
909    #[inline(always)]
910    fn from(variant: Hashcrypt) -> Self {
911        variant as u8 != 0
912    }
913}
914#[doc = "Field `HASHCRYPT` writer - Hash enable set"]
915pub type HashcryptW<'a, REG> = crate::BitWriter<'a, REG, Hashcrypt>;
916impl<'a, REG> HashcryptW<'a, REG>
917where
918    REG: crate::Writable + crate::RegisterSpec,
919{
920    #[doc = "No Effect"]
921    #[inline(always)]
922    pub fn no_effect(self) -> &'a mut crate::W<REG> {
923        self.variant(Hashcrypt::NoEffect)
924    }
925    #[doc = "Sets the ENA0 Bit"]
926    #[inline(always)]
927    pub fn set_ena0_bit(self) -> &'a mut crate::W<REG> {
928        self.variant(Hashcrypt::SetEna0Bit)
929    }
930}
931#[cfg(feature = "debug")]
932impl core::fmt::Debug for crate::generic::Reg<Dmac0ReqEna0SetSpec> {
933    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
934        write!(f, "(not readable)")
935    }
936}
937impl W {
938    #[doc = "Bit 0 - FLEXCOMM0 RX enable set"]
939    #[inline(always)]
940    pub fn flexcomm0_rx(&mut self) -> Flexcomm0RxW<Dmac0ReqEna0SetSpec> {
941        Flexcomm0RxW::new(self, 0)
942    }
943    #[doc = "Bit 1 - FLEXCOMM0 TX enable set"]
944    #[inline(always)]
945    pub fn flexcomm0_tx(&mut self) -> Flexcomm0TxW<Dmac0ReqEna0SetSpec> {
946        Flexcomm0TxW::new(self, 1)
947    }
948    #[doc = "Bit 2 - FLEXCOMM1 RX enable set"]
949    #[inline(always)]
950    pub fn flexcomm1_rx(&mut self) -> Flexcomm1RxW<Dmac0ReqEna0SetSpec> {
951        Flexcomm1RxW::new(self, 2)
952    }
953    #[doc = "Bit 3 - FLEXCOMM1 TX enable set"]
954    #[inline(always)]
955    pub fn flexcomm1_tx(&mut self) -> Flexcomm1TxW<Dmac0ReqEna0SetSpec> {
956        Flexcomm1TxW::new(self, 3)
957    }
958    #[doc = "Bit 4 - FLEXCOMM2 RX enable set"]
959    #[inline(always)]
960    pub fn flexcomm2_rx(&mut self) -> Flexcomm2RxW<Dmac0ReqEna0SetSpec> {
961        Flexcomm2RxW::new(self, 4)
962    }
963    #[doc = "Bit 5 - FLEXCOMM2 TX enable set"]
964    #[inline(always)]
965    pub fn flexcomm2_tx(&mut self) -> Flexcomm2TxW<Dmac0ReqEna0SetSpec> {
966        Flexcomm2TxW::new(self, 5)
967    }
968    #[doc = "Bit 6 - FLEXCOMM3 RX enable set"]
969    #[inline(always)]
970    pub fn flexcomm3_rx(&mut self) -> Flexcomm3RxW<Dmac0ReqEna0SetSpec> {
971        Flexcomm3RxW::new(self, 6)
972    }
973    #[doc = "Bit 7 - FLEXCOMM3 TX enable set"]
974    #[inline(always)]
975    pub fn flexcomm3_tx(&mut self) -> Flexcomm3TxW<Dmac0ReqEna0SetSpec> {
976        Flexcomm3TxW::new(self, 7)
977    }
978    #[doc = "Bit 8 - FLEXCOMM4 RX enable set"]
979    #[inline(always)]
980    pub fn flexcomm4_rx(&mut self) -> Flexcomm4RxW<Dmac0ReqEna0SetSpec> {
981        Flexcomm4RxW::new(self, 8)
982    }
983    #[doc = "Bit 9 - FLEXCOMM4 TX enable set"]
984    #[inline(always)]
985    pub fn flexcomm4_tx(&mut self) -> Flexcomm4TxW<Dmac0ReqEna0SetSpec> {
986        Flexcomm4TxW::new(self, 9)
987    }
988    #[doc = "Bit 10 - FLEXCOMM5 RX enable set"]
989    #[inline(always)]
990    pub fn flexcomm5_rx(&mut self) -> Flexcomm5RxW<Dmac0ReqEna0SetSpec> {
991        Flexcomm5RxW::new(self, 10)
992    }
993    #[doc = "Bit 11 - FLEXCOMM5 TX enable set"]
994    #[inline(always)]
995    pub fn flexcomm5_tx(&mut self) -> Flexcomm5TxW<Dmac0ReqEna0SetSpec> {
996        Flexcomm5TxW::new(self, 11)
997    }
998    #[doc = "Bit 12 - FLEXCOMM6 RX enable set"]
999    #[inline(always)]
1000    pub fn flexcomm6_rx(&mut self) -> Flexcomm6RxW<Dmac0ReqEna0SetSpec> {
1001        Flexcomm6RxW::new(self, 12)
1002    }
1003    #[doc = "Bit 13 - FLEXCOMM6 TX enable set"]
1004    #[inline(always)]
1005    pub fn flexcomm6_tx(&mut self) -> Flexcomm6TxW<Dmac0ReqEna0SetSpec> {
1006        Flexcomm6TxW::new(self, 13)
1007    }
1008    #[doc = "Bit 14 - FLEXCOMM7 RX enable set"]
1009    #[inline(always)]
1010    pub fn flexcomm7_rx(&mut self) -> Flexcomm7RxW<Dmac0ReqEna0SetSpec> {
1011        Flexcomm7RxW::new(self, 14)
1012    }
1013    #[doc = "Bit 15 - FLEXCOMM7 TX enable set"]
1014    #[inline(always)]
1015    pub fn flexcomm7_tx(&mut self) -> Flexcomm7TxW<Dmac0ReqEna0SetSpec> {
1016        Flexcomm7TxW::new(self, 15)
1017    }
1018    #[doc = "Bit 16 - DMIC0 channel 0 enable set"]
1019    #[inline(always)]
1020    pub fn dmic0ch0(&mut self) -> Dmic0ch0W<Dmac0ReqEna0SetSpec> {
1021        Dmic0ch0W::new(self, 16)
1022    }
1023    #[doc = "Bit 17 - DMIC0 channel 1 enable set"]
1024    #[inline(always)]
1025    pub fn dmic0ch1(&mut self) -> Dmic0ch1W<Dmac0ReqEna0SetSpec> {
1026        Dmic0ch1W::new(self, 17)
1027    }
1028    #[doc = "Bit 18 - DMIC0 channel 2 enable set"]
1029    #[inline(always)]
1030    pub fn dmic0ch2(&mut self) -> Dmic0ch2W<Dmac0ReqEna0SetSpec> {
1031        Dmic0ch2W::new(self, 18)
1032    }
1033    #[doc = "Bit 19 - DMIC0 channel 3 enable set"]
1034    #[inline(always)]
1035    pub fn dmic0ch3(&mut self) -> Dmic0ch3W<Dmac0ReqEna0SetSpec> {
1036        Dmic0ch3W::new(self, 19)
1037    }
1038    #[doc = "Bit 20 - DMIC0 channel 4 enable set"]
1039    #[inline(always)]
1040    pub fn dmic0ch4(&mut self) -> Dmic0ch4W<Dmac0ReqEna0SetSpec> {
1041        Dmic0ch4W::new(self, 20)
1042    }
1043    #[doc = "Bit 21 - DMIC0 channel 5 enable set"]
1044    #[inline(always)]
1045    pub fn dmic0ch5(&mut self) -> Dmic0ch5W<Dmac0ReqEna0SetSpec> {
1046        Dmic0ch5W::new(self, 21)
1047    }
1048    #[doc = "Bit 22 - DMIC0 channel 6 enable set"]
1049    #[inline(always)]
1050    pub fn dmic0ch6(&mut self) -> Dmic0ch6W<Dmac0ReqEna0SetSpec> {
1051        Dmic0ch6W::new(self, 22)
1052    }
1053    #[doc = "Bit 23 - DMIC0 channel 7 enable set"]
1054    #[inline(always)]
1055    pub fn dmic0ch7(&mut self) -> Dmic0ch7W<Dmac0ReqEna0SetSpec> {
1056        Dmic0ch7W::new(self, 23)
1057    }
1058    #[doc = "Bit 24 - I3C RX enable set"]
1059    #[inline(always)]
1060    pub fn i3c0_rx(&mut self) -> I3c0RxW<Dmac0ReqEna0SetSpec> {
1061        I3c0RxW::new(self, 24)
1062    }
1063    #[doc = "Bit 25 - I3C TX enable set"]
1064    #[inline(always)]
1065    pub fn i3c0_tx(&mut self) -> I3c0TxW<Dmac0ReqEna0SetSpec> {
1066        I3c0TxW::new(self, 25)
1067    }
1068    #[doc = "Bit 26 - FLEXCOMM14 TX enable set"]
1069    #[inline(always)]
1070    pub fn flexcomm14_rx(&mut self) -> Flexcomm14RxW<Dmac0ReqEna0SetSpec> {
1071        Flexcomm14RxW::new(self, 26)
1072    }
1073    #[doc = "Bit 27 - FLEXCOMM15 RX enable set"]
1074    #[inline(always)]
1075    pub fn flexcomm14_tx(&mut self) -> Flexcomm14TxW<Dmac0ReqEna0SetSpec> {
1076        Flexcomm14TxW::new(self, 27)
1077    }
1078    #[doc = "Bit 30 - Hash enable set"]
1079    #[inline(always)]
1080    pub fn hashcrypt(&mut self) -> HashcryptW<Dmac0ReqEna0SetSpec> {
1081        HashcryptW::new(self, 30)
1082    }
1083}
1084#[doc = "DMAC0 request enable set 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmac0_req_ena0_set::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1085pub struct Dmac0ReqEna0SetSpec;
1086impl crate::RegisterSpec for Dmac0ReqEna0SetSpec {
1087    type Ux = u32;
1088}
1089#[doc = "`write(|w| ..)` method takes [`dmac0_req_ena0_set::W`](W) writer structure"]
1090impl crate::Writable for Dmac0ReqEna0SetSpec {
1091    type Safety = crate::Unsafe;
1092    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1093    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1094}
1095#[doc = "`reset()` method sets DMAC0_REQ_ENA0_SET to value 0"]
1096impl crate::Resettable for Dmac0ReqEna0SetSpec {
1097    const RESET_VALUE: u32 = 0;
1098}
mimxrt685s_pac/inputmux/dmac0_req_ena0_set.rs

mimxrt685s_pac/inputmux/
dmac0_req_ena0_set.rs
