mimxrt685s_pac/inputmux/ct32bit_cap/
ct32bit_cap_sel.rs

1#[doc = "Register `CT32BIT_CAP_SEL%s` reader"]
2pub type R = crate::R<Ct32bitCapSelSpec>;
3#[doc = "Register `CT32BIT_CAP_SEL%s` writer"]
4pub type W = crate::W<Ct32bitCapSelSpec>;
5#[doc = "Counter Timer m, Capture Port Input n 19:1 Mux Select. . .\n\nValue on reset: 31"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum CapnSel {
10    #[doc = "0: CT_INP0"]
11    CtInp0 = 0,
12    #[doc = "1: CT_INP1"]
13    CtInp1 = 1,
14    #[doc = "2: CT_INP2"]
15    CtInp2 = 2,
16    #[doc = "3: CT_INP3"]
17    CtInp3 = 3,
18    #[doc = "4: CT_INP4"]
19    CtInp4 = 4,
20    #[doc = "5: CT_INP5"]
21    CtInp5 = 5,
22    #[doc = "6: CT_INP6"]
23    CtInp6 = 6,
24    #[doc = "7: CT_INP7"]
25    CtInp7 = 7,
26    #[doc = "8: CT_INP8"]
27    CtInp8 = 8,
28    #[doc = "9: CT_INP9"]
29    CtInp9 = 9,
30    #[doc = "10: CT_INP10"]
31    CtInp10 = 10,
32    #[doc = "11: CT_INP11"]
33    CtInp11 = 11,
34    #[doc = "12: CT_INP12"]
35    CtInp12 = 12,
36    #[doc = "13: CT_INP13"]
37    CtInp13 = 13,
38    #[doc = "14: CT_INP14"]
39    CtInp14 = 14,
40    #[doc = "15: CT_INP15"]
41    CtInp15 = 15,
42    #[doc = "16: SHARED I2S0_WS"]
43    SharedI2s0Ws = 16,
44    #[doc = "17: SHARED I2S1_WS"]
45    SharedI2s1Ws = 17,
46    #[doc = "18: USB1_FRAME_TOGGLE"]
47    Usb1FrameToggle = 18,
48}
49impl From<CapnSel> for u8 {
50    #[inline(always)]
51    fn from(variant: CapnSel) -> Self {
52        variant as _
53    }
54}
55impl crate::FieldSpec for CapnSel {
56    type Ux = u8;
57}
58impl crate::IsEnum for CapnSel {}
59#[doc = "Field `CAPn_SEL` reader - Counter Timer m, Capture Port Input n 19:1 Mux Select. . ."]
60pub type CapnSelR = crate::FieldReader<CapnSel>;
61impl CapnSelR {
62    #[doc = "Get enumerated values variant"]
63    #[inline(always)]
64    pub const fn variant(&self) -> Option<CapnSel> {
65        match self.bits {
66            0 => Some(CapnSel::CtInp0),
67            1 => Some(CapnSel::CtInp1),
68            2 => Some(CapnSel::CtInp2),
69            3 => Some(CapnSel::CtInp3),
70            4 => Some(CapnSel::CtInp4),
71            5 => Some(CapnSel::CtInp5),
72            6 => Some(CapnSel::CtInp6),
73            7 => Some(CapnSel::CtInp7),
74            8 => Some(CapnSel::CtInp8),
75            9 => Some(CapnSel::CtInp9),
76            10 => Some(CapnSel::CtInp10),
77            11 => Some(CapnSel::CtInp11),
78            12 => Some(CapnSel::CtInp12),
79            13 => Some(CapnSel::CtInp13),
80            14 => Some(CapnSel::CtInp14),
81            15 => Some(CapnSel::CtInp15),
82            16 => Some(CapnSel::SharedI2s0Ws),
83            17 => Some(CapnSel::SharedI2s1Ws),
84            18 => Some(CapnSel::Usb1FrameToggle),
85            _ => None,
86        }
87    }
88    #[doc = "CT_INP0"]
89    #[inline(always)]
90    pub fn is_ct_inp0(&self) -> bool {
91        *self == CapnSel::CtInp0
92    }
93    #[doc = "CT_INP1"]
94    #[inline(always)]
95    pub fn is_ct_inp1(&self) -> bool {
96        *self == CapnSel::CtInp1
97    }
98    #[doc = "CT_INP2"]
99    #[inline(always)]
100    pub fn is_ct_inp2(&self) -> bool {
101        *self == CapnSel::CtInp2
102    }
103    #[doc = "CT_INP3"]
104    #[inline(always)]
105    pub fn is_ct_inp3(&self) -> bool {
106        *self == CapnSel::CtInp3
107    }
108    #[doc = "CT_INP4"]
109    #[inline(always)]
110    pub fn is_ct_inp4(&self) -> bool {
111        *self == CapnSel::CtInp4
112    }
113    #[doc = "CT_INP5"]
114    #[inline(always)]
115    pub fn is_ct_inp5(&self) -> bool {
116        *self == CapnSel::CtInp5
117    }
118    #[doc = "CT_INP6"]
119    #[inline(always)]
120    pub fn is_ct_inp6(&self) -> bool {
121        *self == CapnSel::CtInp6
122    }
123    #[doc = "CT_INP7"]
124    #[inline(always)]
125    pub fn is_ct_inp7(&self) -> bool {
126        *self == CapnSel::CtInp7
127    }
128    #[doc = "CT_INP8"]
129    #[inline(always)]
130    pub fn is_ct_inp8(&self) -> bool {
131        *self == CapnSel::CtInp8
132    }
133    #[doc = "CT_INP9"]
134    #[inline(always)]
135    pub fn is_ct_inp9(&self) -> bool {
136        *self == CapnSel::CtInp9
137    }
138    #[doc = "CT_INP10"]
139    #[inline(always)]
140    pub fn is_ct_inp10(&self) -> bool {
141        *self == CapnSel::CtInp10
142    }
143    #[doc = "CT_INP11"]
144    #[inline(always)]
145    pub fn is_ct_inp11(&self) -> bool {
146        *self == CapnSel::CtInp11
147    }
148    #[doc = "CT_INP12"]
149    #[inline(always)]
150    pub fn is_ct_inp12(&self) -> bool {
151        *self == CapnSel::CtInp12
152    }
153    #[doc = "CT_INP13"]
154    #[inline(always)]
155    pub fn is_ct_inp13(&self) -> bool {
156        *self == CapnSel::CtInp13
157    }
158    #[doc = "CT_INP14"]
159    #[inline(always)]
160    pub fn is_ct_inp14(&self) -> bool {
161        *self == CapnSel::CtInp14
162    }
163    #[doc = "CT_INP15"]
164    #[inline(always)]
165    pub fn is_ct_inp15(&self) -> bool {
166        *self == CapnSel::CtInp15
167    }
168    #[doc = "SHARED I2S0_WS"]
169    #[inline(always)]
170    pub fn is_shared_i2s0_ws(&self) -> bool {
171        *self == CapnSel::SharedI2s0Ws
172    }
173    #[doc = "SHARED I2S1_WS"]
174    #[inline(always)]
175    pub fn is_shared_i2s1_ws(&self) -> bool {
176        *self == CapnSel::SharedI2s1Ws
177    }
178    #[doc = "USB1_FRAME_TOGGLE"]
179    #[inline(always)]
180    pub fn is_usb1_frame_toggle(&self) -> bool {
181        *self == CapnSel::Usb1FrameToggle
182    }
183}
184#[doc = "Field `CAPn_SEL` writer - Counter Timer m, Capture Port Input n 19:1 Mux Select. . ."]
185pub type CapnSelW<'a, REG> = crate::FieldWriter<'a, REG, 5, CapnSel>;
186impl<'a, REG> CapnSelW<'a, REG>
187where
188    REG: crate::Writable + crate::RegisterSpec,
189    REG::Ux: From<u8>,
190{
191    #[doc = "CT_INP0"]
192    #[inline(always)]
193    pub fn ct_inp0(self) -> &'a mut crate::W<REG> {
194        self.variant(CapnSel::CtInp0)
195    }
196    #[doc = "CT_INP1"]
197    #[inline(always)]
198    pub fn ct_inp1(self) -> &'a mut crate::W<REG> {
199        self.variant(CapnSel::CtInp1)
200    }
201    #[doc = "CT_INP2"]
202    #[inline(always)]
203    pub fn ct_inp2(self) -> &'a mut crate::W<REG> {
204        self.variant(CapnSel::CtInp2)
205    }
206    #[doc = "CT_INP3"]
207    #[inline(always)]
208    pub fn ct_inp3(self) -> &'a mut crate::W<REG> {
209        self.variant(CapnSel::CtInp3)
210    }
211    #[doc = "CT_INP4"]
212    #[inline(always)]
213    pub fn ct_inp4(self) -> &'a mut crate::W<REG> {
214        self.variant(CapnSel::CtInp4)
215    }
216    #[doc = "CT_INP5"]
217    #[inline(always)]
218    pub fn ct_inp5(self) -> &'a mut crate::W<REG> {
219        self.variant(CapnSel::CtInp5)
220    }
221    #[doc = "CT_INP6"]
222    #[inline(always)]
223    pub fn ct_inp6(self) -> &'a mut crate::W<REG> {
224        self.variant(CapnSel::CtInp6)
225    }
226    #[doc = "CT_INP7"]
227    #[inline(always)]
228    pub fn ct_inp7(self) -> &'a mut crate::W<REG> {
229        self.variant(CapnSel::CtInp7)
230    }
231    #[doc = "CT_INP8"]
232    #[inline(always)]
233    pub fn ct_inp8(self) -> &'a mut crate::W<REG> {
234        self.variant(CapnSel::CtInp8)
235    }
236    #[doc = "CT_INP9"]
237    #[inline(always)]
238    pub fn ct_inp9(self) -> &'a mut crate::W<REG> {
239        self.variant(CapnSel::CtInp9)
240    }
241    #[doc = "CT_INP10"]
242    #[inline(always)]
243    pub fn ct_inp10(self) -> &'a mut crate::W<REG> {
244        self.variant(CapnSel::CtInp10)
245    }
246    #[doc = "CT_INP11"]
247    #[inline(always)]
248    pub fn ct_inp11(self) -> &'a mut crate::W<REG> {
249        self.variant(CapnSel::CtInp11)
250    }
251    #[doc = "CT_INP12"]
252    #[inline(always)]
253    pub fn ct_inp12(self) -> &'a mut crate::W<REG> {
254        self.variant(CapnSel::CtInp12)
255    }
256    #[doc = "CT_INP13"]
257    #[inline(always)]
258    pub fn ct_inp13(self) -> &'a mut crate::W<REG> {
259        self.variant(CapnSel::CtInp13)
260    }
261    #[doc = "CT_INP14"]
262    #[inline(always)]
263    pub fn ct_inp14(self) -> &'a mut crate::W<REG> {
264        self.variant(CapnSel::CtInp14)
265    }
266    #[doc = "CT_INP15"]
267    #[inline(always)]
268    pub fn ct_inp15(self) -> &'a mut crate::W<REG> {
269        self.variant(CapnSel::CtInp15)
270    }
271    #[doc = "SHARED I2S0_WS"]
272    #[inline(always)]
273    pub fn shared_i2s0_ws(self) -> &'a mut crate::W<REG> {
274        self.variant(CapnSel::SharedI2s0Ws)
275    }
276    #[doc = "SHARED I2S1_WS"]
277    #[inline(always)]
278    pub fn shared_i2s1_ws(self) -> &'a mut crate::W<REG> {
279        self.variant(CapnSel::SharedI2s1Ws)
280    }
281    #[doc = "USB1_FRAME_TOGGLE"]
282    #[inline(always)]
283    pub fn usb1_frame_toggle(self) -> &'a mut crate::W<REG> {
284        self.variant(CapnSel::Usb1FrameToggle)
285    }
286}
287impl R {
288    #[doc = "Bits 0:4 - Counter Timer m, Capture Port Input n 19:1 Mux Select. . ."]
289    #[inline(always)]
290    pub fn capn_sel(&self) -> CapnSelR {
291        CapnSelR::new((self.bits & 0x1f) as u8)
292    }
293}
294#[cfg(feature = "debug")]
295impl core::fmt::Debug for R {
296    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
297        f.debug_struct("CT32BIT_CAP_SEL")
298            .field("capn_sel", &self.capn_sel())
299            .finish()
300    }
301}
302impl W {
303    #[doc = "Bits 0:4 - Counter Timer m, Capture Port Input n 19:1 Mux Select. . ."]
304    #[inline(always)]
305    pub fn capn_sel(&mut self) -> CapnSelW<Ct32bitCapSelSpec> {
306        CapnSelW::new(self, 0)
307    }
308}
309#[doc = "CT32BIT N Counter Timer Capture Trigger Multiplexers M\n\nYou can [`read`](crate::Reg::read) this register and get [`ct32bit_cap_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ct32bit_cap_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
310pub struct Ct32bitCapSelSpec;
311impl crate::RegisterSpec for Ct32bitCapSelSpec {
312    type Ux = u32;
313}
314#[doc = "`read()` method returns [`ct32bit_cap_sel::R`](R) reader structure"]
315impl crate::Readable for Ct32bitCapSelSpec {}
316#[doc = "`write(|w| ..)` method takes [`ct32bit_cap_sel::W`](W) writer structure"]
317impl crate::Writable for Ct32bitCapSelSpec {
318    type Safety = crate::Unsafe;
319    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
320    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
321}
322#[doc = "`reset()` method sets CT32BIT_CAP_SEL%s to value 0x1f"]
323impl crate::Resettable for Ct32bitCapSelSpec {
324    const RESET_VALUE: u32 = 0x1f;
325}
mimxrt685s_pac/inputmux/ct32bit_cap/ct32bit_cap_sel.rs

mimxrt685s_pac/inputmux/ct32bit_cap/
ct32bit_cap_sel.rs
