mimxrt685s_pac/i3c/
mwmsg_sdr_control.rs

1#[doc = "Register `MWMSG_SDR_CONTROL` writer"]
2pub type W = crate::W<MwmsgSdrControlSpec>;
3#[doc = "Direction\n\nValue on reset: 0"]
4#[cfg_attr(feature = "defmt", derive(defmt::Format))]
5#[derive(Clone, Copy, Debug, PartialEq, Eq)]
6pub enum Dir {
7    #[doc = "0: Write"]
8    Write = 0,
9    #[doc = "1: Read"]
10    Read = 1,
11}
12impl From<Dir> for bool {
13    #[inline(always)]
14    fn from(variant: Dir) -> Self {
15        variant as u8 != 0
16    }
17}
18#[doc = "Field `DIR` writer - Direction"]
19pub type DirW<'a, REG> = crate::BitWriter<'a, REG, Dir>;
20impl<'a, REG> DirW<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    #[doc = "Write"]
25    #[inline(always)]
26    pub fn write(self) -> &'a mut crate::W<REG> {
27        self.variant(Dir::Write)
28    }
29    #[doc = "Read"]
30    #[inline(always)]
31    pub fn read(self) -> &'a mut crate::W<REG> {
32        self.variant(Dir::Read)
33    }
34}
35#[doc = "Field `ADDR` writer - Address to be written to"]
36pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
37#[doc = "Field `END` writer - End of SDR message"]
38pub type EndW<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "I2C\n\nValue on reset: 0"]
40#[cfg_attr(feature = "defmt", derive(defmt::Format))]
41#[derive(Clone, Copy, Debug, PartialEq, Eq)]
42pub enum I2c {
43    #[doc = "0: I3C message"]
44    I3cmessage = 0,
45    #[doc = "1: I2C message"]
46    I2cmessage = 1,
47}
48impl From<I2c> for bool {
49    #[inline(always)]
50    fn from(variant: I2c) -> Self {
51        variant as u8 != 0
52    }
53}
54#[doc = "Field `I2C` writer - I2C"]
55pub type I2cW<'a, REG> = crate::BitWriter<'a, REG, I2c>;
56impl<'a, REG> I2cW<'a, REG>
57where
58    REG: crate::Writable + crate::RegisterSpec,
59{
60    #[doc = "I3C message"]
61    #[inline(always)]
62    pub fn i3cmessage(self) -> &'a mut crate::W<REG> {
63        self.variant(I2c::I3cmessage)
64    }
65    #[doc = "I2C message"]
66    #[inline(always)]
67    pub fn i2cmessage(self) -> &'a mut crate::W<REG> {
68        self.variant(I2c::I2cmessage)
69    }
70}
71#[doc = "Field `LEN` writer - Length"]
72pub type LenW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
73#[cfg(feature = "debug")]
74impl core::fmt::Debug for crate::generic::Reg<MwmsgSdrControlSpec> {
75    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
76        write!(f, "(not readable)")
77    }
78}
79impl W {
80    #[doc = "Bit 0 - Direction"]
81    #[inline(always)]
82    pub fn dir(&mut self) -> DirW<MwmsgSdrControlSpec> {
83        DirW::new(self, 0)
84    }
85    #[doc = "Bits 1:7 - Address to be written to"]
86    #[inline(always)]
87    pub fn addr(&mut self) -> AddrW<MwmsgSdrControlSpec> {
88        AddrW::new(self, 1)
89    }
90    #[doc = "Bit 8 - End of SDR message"]
91    #[inline(always)]
92    pub fn end(&mut self) -> EndW<MwmsgSdrControlSpec> {
93        EndW::new(self, 8)
94    }
95    #[doc = "Bit 10 - I2C"]
96    #[inline(always)]
97    pub fn i2c(&mut self) -> I2cW<MwmsgSdrControlSpec> {
98        I2cW::new(self, 10)
99    }
100    #[doc = "Bits 11:15 - Length"]
101    #[inline(always)]
102    pub fn len(&mut self) -> LenW<MwmsgSdrControlSpec> {
103        LenW::new(self, 11)
104    }
105}
106#[doc = "Master Write Message in SDR mode\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mwmsg_sdr_control::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
107pub struct MwmsgSdrControlSpec;
108impl crate::RegisterSpec for MwmsgSdrControlSpec {
109    type Ux = u32;
110}
111#[doc = "`write(|w| ..)` method takes [`mwmsg_sdr_control::W`](W) writer structure"]
112impl crate::Writable for MwmsgSdrControlSpec {
113    type Safety = crate::Unsafe;
114    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
115    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
116}
117#[doc = "`reset()` method sets MWMSG_SDR_CONTROL to value 0"]
118impl crate::Resettable for MwmsgSdrControlSpec {
119    const RESET_VALUE: u32 = 0;
120}
mimxrt685s_pac/i3c/mwmsg_sdr_control.rs

mimxrt685s_pac/i3c/
mwmsg_sdr_control.rs
