1#[doc = "Register `CFG1` reader"]
2pub type R = crate::R<Cfg1Spec>;
3#[doc = "Register `CFG1` writer"]
4pub type W = crate::W<Cfg1Spec>;
5#[doc = "Main enable for I 2S function in this Flexcomm\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Mainenable {
9 #[doc = "0: All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled."]
10 Disabled = 0,
11 #[doc = "1: This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits."]
12 Enabled = 1,
13}
14impl From<Mainenable> for bool {
15 #[inline(always)]
16 fn from(variant: Mainenable) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `MAINENABLE` reader - Main enable for I 2S function in this Flexcomm"]
21pub type MainenableR = crate::BitReader<Mainenable>;
22impl MainenableR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> Mainenable {
26 match self.bits {
27 false => Mainenable::Disabled,
28 true => Mainenable::Enabled,
29 }
30 }
31 #[doc = "All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled."]
32 #[inline(always)]
33 pub fn is_disabled(&self) -> bool {
34 *self == Mainenable::Disabled
35 }
36 #[doc = "This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits."]
37 #[inline(always)]
38 pub fn is_enabled(&self) -> bool {
39 *self == Mainenable::Enabled
40 }
41}
42#[doc = "Field `MAINENABLE` writer - Main enable for I 2S function in this Flexcomm"]
43pub type MainenableW<'a, REG> = crate::BitWriter<'a, REG, Mainenable>;
44impl<'a, REG> MainenableW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled."]
49 #[inline(always)]
50 pub fn disabled(self) -> &'a mut crate::W<REG> {
51 self.variant(Mainenable::Disabled)
52 }
53 #[doc = "This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits."]
54 #[inline(always)]
55 pub fn enabled(self) -> &'a mut crate::W<REG> {
56 self.variant(Mainenable::Enabled)
57 }
58}
59#[doc = "Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame.\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Datapause {
63 #[doc = "0: Normal operation, or resuming normal operation at the next frame if the I2S has already been paused."]
64 Normal = 0,
65 #[doc = "1: A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1."]
66 Pause = 1,
67}
68impl From<Datapause> for bool {
69 #[inline(always)]
70 fn from(variant: Datapause) -> Self {
71 variant as u8 != 0
72 }
73}
74#[doc = "Field `DATAPAUSE` reader - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame."]
75pub type DatapauseR = crate::BitReader<Datapause>;
76impl DatapauseR {
77 #[doc = "Get enumerated values variant"]
78 #[inline(always)]
79 pub const fn variant(&self) -> Datapause {
80 match self.bits {
81 false => Datapause::Normal,
82 true => Datapause::Pause,
83 }
84 }
85 #[doc = "Normal operation, or resuming normal operation at the next frame if the I2S has already been paused."]
86 #[inline(always)]
87 pub fn is_normal(&self) -> bool {
88 *self == Datapause::Normal
89 }
90 #[doc = "A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1."]
91 #[inline(always)]
92 pub fn is_pause(&self) -> bool {
93 *self == Datapause::Pause
94 }
95}
96#[doc = "Field `DATAPAUSE` writer - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame."]
97pub type DatapauseW<'a, REG> = crate::BitWriter<'a, REG, Datapause>;
98impl<'a, REG> DatapauseW<'a, REG>
99where
100 REG: crate::Writable + crate::RegisterSpec,
101{
102 #[doc = "Normal operation, or resuming normal operation at the next frame if the I2S has already been paused."]
103 #[inline(always)]
104 pub fn normal(self) -> &'a mut crate::W<REG> {
105 self.variant(Datapause::Normal)
106 }
107 #[doc = "A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1."]
108 #[inline(always)]
109 pub fn pause(self) -> &'a mut crate::W<REG> {
110 self.variant(Datapause::Pause)
111 }
112}
113#[doc = "Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm.\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116#[repr(u8)]
117pub enum Paircount {
118 #[doc = "0: 1 I2S channel pairs in this flexcomm"]
119 Pairs1 = 0,
120 #[doc = "1: 2 I2S channel pairs in this flexcomm"]
121 Pairs2 = 1,
122 #[doc = "2: 3 I2S channel pairs in this flexcomm"]
123 Pairs3 = 2,
124 #[doc = "3: 4 I2S channel pairs in this flexcomm"]
125 Pairs4 = 3,
126}
127impl From<Paircount> for u8 {
128 #[inline(always)]
129 fn from(variant: Paircount) -> Self {
130 variant as _
131 }
132}
133impl crate::FieldSpec for Paircount {
134 type Ux = u8;
135}
136impl crate::IsEnum for Paircount {}
137#[doc = "Field `PAIRCOUNT` reader - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm."]
138pub type PaircountR = crate::FieldReader<Paircount>;
139impl PaircountR {
140 #[doc = "Get enumerated values variant"]
141 #[inline(always)]
142 pub const fn variant(&self) -> Paircount {
143 match self.bits {
144 0 => Paircount::Pairs1,
145 1 => Paircount::Pairs2,
146 2 => Paircount::Pairs3,
147 3 => Paircount::Pairs4,
148 _ => unreachable!(),
149 }
150 }
151 #[doc = "1 I2S channel pairs in this flexcomm"]
152 #[inline(always)]
153 pub fn is_pairs_1(&self) -> bool {
154 *self == Paircount::Pairs1
155 }
156 #[doc = "2 I2S channel pairs in this flexcomm"]
157 #[inline(always)]
158 pub fn is_pairs_2(&self) -> bool {
159 *self == Paircount::Pairs2
160 }
161 #[doc = "3 I2S channel pairs in this flexcomm"]
162 #[inline(always)]
163 pub fn is_pairs_3(&self) -> bool {
164 *self == Paircount::Pairs3
165 }
166 #[doc = "4 I2S channel pairs in this flexcomm"]
167 #[inline(always)]
168 pub fn is_pairs_4(&self) -> bool {
169 *self == Paircount::Pairs4
170 }
171}
172#[doc = "Field `PAIRCOUNT` writer - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm."]
173pub type PaircountW<'a, REG> = crate::FieldWriter<'a, REG, 2, Paircount, crate::Safe>;
174impl<'a, REG> PaircountW<'a, REG>
175where
176 REG: crate::Writable + crate::RegisterSpec,
177 REG::Ux: From<u8>,
178{
179 #[doc = "1 I2S channel pairs in this flexcomm"]
180 #[inline(always)]
181 pub fn pairs_1(self) -> &'a mut crate::W<REG> {
182 self.variant(Paircount::Pairs1)
183 }
184 #[doc = "2 I2S channel pairs in this flexcomm"]
185 #[inline(always)]
186 pub fn pairs_2(self) -> &'a mut crate::W<REG> {
187 self.variant(Paircount::Pairs2)
188 }
189 #[doc = "3 I2S channel pairs in this flexcomm"]
190 #[inline(always)]
191 pub fn pairs_3(self) -> &'a mut crate::W<REG> {
192 self.variant(Paircount::Pairs3)
193 }
194 #[doc = "4 I2S channel pairs in this flexcomm"]
195 #[inline(always)]
196 pub fn pairs_4(self) -> &'a mut crate::W<REG> {
197 self.variant(Paircount::Pairs4)
198 }
199}
200#[doc = "Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm.\n\nValue on reset: 0"]
201#[cfg_attr(feature = "defmt", derive(defmt::Format))]
202#[derive(Clone, Copy, Debug, PartialEq, Eq)]
203#[repr(u8)]
204pub enum Mstslvcfg {
205 #[doc = "0: Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data."]
206 NormalSlaveMode = 0,
207 #[doc = "1: WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock."]
208 WsSyncMaster = 1,
209 #[doc = "2: Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data."]
210 MasterUsingSck = 2,
211 #[doc = "3: Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices."]
212 NormalMaster = 3,
213}
214impl From<Mstslvcfg> for u8 {
215 #[inline(always)]
216 fn from(variant: Mstslvcfg) -> Self {
217 variant as _
218 }
219}
220impl crate::FieldSpec for Mstslvcfg {
221 type Ux = u8;
222}
223impl crate::IsEnum for Mstslvcfg {}
224#[doc = "Field `MSTSLVCFG` reader - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm."]
225pub type MstslvcfgR = crate::FieldReader<Mstslvcfg>;
226impl MstslvcfgR {
227 #[doc = "Get enumerated values variant"]
228 #[inline(always)]
229 pub const fn variant(&self) -> Mstslvcfg {
230 match self.bits {
231 0 => Mstslvcfg::NormalSlaveMode,
232 1 => Mstslvcfg::WsSyncMaster,
233 2 => Mstslvcfg::MasterUsingSck,
234 3 => Mstslvcfg::NormalMaster,
235 _ => unreachable!(),
236 }
237 }
238 #[doc = "Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data."]
239 #[inline(always)]
240 pub fn is_normal_slave_mode(&self) -> bool {
241 *self == Mstslvcfg::NormalSlaveMode
242 }
243 #[doc = "WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock."]
244 #[inline(always)]
245 pub fn is_ws_sync_master(&self) -> bool {
246 *self == Mstslvcfg::WsSyncMaster
247 }
248 #[doc = "Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data."]
249 #[inline(always)]
250 pub fn is_master_using_sck(&self) -> bool {
251 *self == Mstslvcfg::MasterUsingSck
252 }
253 #[doc = "Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices."]
254 #[inline(always)]
255 pub fn is_normal_master(&self) -> bool {
256 *self == Mstslvcfg::NormalMaster
257 }
258}
259#[doc = "Field `MSTSLVCFG` writer - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm."]
260pub type MstslvcfgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mstslvcfg, crate::Safe>;
261impl<'a, REG> MstslvcfgW<'a, REG>
262where
263 REG: crate::Writable + crate::RegisterSpec,
264 REG::Ux: From<u8>,
265{
266 #[doc = "Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data."]
267 #[inline(always)]
268 pub fn normal_slave_mode(self) -> &'a mut crate::W<REG> {
269 self.variant(Mstslvcfg::NormalSlaveMode)
270 }
271 #[doc = "WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock."]
272 #[inline(always)]
273 pub fn ws_sync_master(self) -> &'a mut crate::W<REG> {
274 self.variant(Mstslvcfg::WsSyncMaster)
275 }
276 #[doc = "Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data."]
277 #[inline(always)]
278 pub fn master_using_sck(self) -> &'a mut crate::W<REG> {
279 self.variant(Mstslvcfg::MasterUsingSck)
280 }
281 #[doc = "Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices."]
282 #[inline(always)]
283 pub fn normal_master(self) -> &'a mut crate::W<REG> {
284 self.variant(Mstslvcfg::NormalMaster)
285 }
286}
287#[doc = "Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples.\n\nValue on reset: 0"]
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290#[repr(u8)]
291pub enum Mode {
292 #[doc = "0: I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right."]
293 ClassicMode = 0,
294 #[doc = "1: DSP mode where WS has a 50% duty cycle. See remark for mode 0."]
295 DspModeWs50Dutycycle = 1,
296 #[doc = "2: DSP mode where WS has a one clock long pulse at the beginning of each data frame."]
297 DspModeWs1Clock = 2,
298 #[doc = "3: DSP mode where WS has a one data slot long pulse at the beginning of each data frame."]
299 DspModeWs1Data = 3,
300}
301impl From<Mode> for u8 {
302 #[inline(always)]
303 fn from(variant: Mode) -> Self {
304 variant as _
305 }
306}
307impl crate::FieldSpec for Mode {
308 type Ux = u8;
309}
310impl crate::IsEnum for Mode {}
311#[doc = "Field `MODE` reader - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples."]
312pub type ModeR = crate::FieldReader<Mode>;
313impl ModeR {
314 #[doc = "Get enumerated values variant"]
315 #[inline(always)]
316 pub const fn variant(&self) -> Mode {
317 match self.bits {
318 0 => Mode::ClassicMode,
319 1 => Mode::DspModeWs50Dutycycle,
320 2 => Mode::DspModeWs1Clock,
321 3 => Mode::DspModeWs1Data,
322 _ => unreachable!(),
323 }
324 }
325 #[doc = "I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right."]
326 #[inline(always)]
327 pub fn is_classic_mode(&self) -> bool {
328 *self == Mode::ClassicMode
329 }
330 #[doc = "DSP mode where WS has a 50% duty cycle. See remark for mode 0."]
331 #[inline(always)]
332 pub fn is_dsp_mode_ws_50_dutycycle(&self) -> bool {
333 *self == Mode::DspModeWs50Dutycycle
334 }
335 #[doc = "DSP mode where WS has a one clock long pulse at the beginning of each data frame."]
336 #[inline(always)]
337 pub fn is_dsp_mode_ws_1_clock(&self) -> bool {
338 *self == Mode::DspModeWs1Clock
339 }
340 #[doc = "DSP mode where WS has a one data slot long pulse at the beginning of each data frame."]
341 #[inline(always)]
342 pub fn is_dsp_mode_ws_1_data(&self) -> bool {
343 *self == Mode::DspModeWs1Data
344 }
345}
346#[doc = "Field `MODE` writer - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples."]
347pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mode, crate::Safe>;
348impl<'a, REG> ModeW<'a, REG>
349where
350 REG: crate::Writable + crate::RegisterSpec,
351 REG::Ux: From<u8>,
352{
353 #[doc = "I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right."]
354 #[inline(always)]
355 pub fn classic_mode(self) -> &'a mut crate::W<REG> {
356 self.variant(Mode::ClassicMode)
357 }
358 #[doc = "DSP mode where WS has a 50% duty cycle. See remark for mode 0."]
359 #[inline(always)]
360 pub fn dsp_mode_ws_50_dutycycle(self) -> &'a mut crate::W<REG> {
361 self.variant(Mode::DspModeWs50Dutycycle)
362 }
363 #[doc = "DSP mode where WS has a one clock long pulse at the beginning of each data frame."]
364 #[inline(always)]
365 pub fn dsp_mode_ws_1_clock(self) -> &'a mut crate::W<REG> {
366 self.variant(Mode::DspModeWs1Clock)
367 }
368 #[doc = "DSP mode where WS has a one data slot long pulse at the beginning of each data frame."]
369 #[inline(always)]
370 pub fn dsp_mode_ws_1_data(self) -> &'a mut crate::W<REG> {
371 self.variant(Mode::DspModeWs1Data)
372 }
373}
374#[doc = "Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed.\n\nValue on reset: 0"]
375#[cfg_attr(feature = "defmt", derive(defmt::Format))]
376#[derive(Clone, Copy, Debug, PartialEq, Eq)]
377pub enum Rightlow {
378 #[doc = "0: The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel."]
379 RightHigh = 0,
380 #[doc = "1: The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel."]
381 RightLow = 1,
382}
383impl From<Rightlow> for bool {
384 #[inline(always)]
385 fn from(variant: Rightlow) -> Self {
386 variant as u8 != 0
387 }
388}
389#[doc = "Field `RIGHTLOW` reader - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed."]
390pub type RightlowR = crate::BitReader<Rightlow>;
391impl RightlowR {
392 #[doc = "Get enumerated values variant"]
393 #[inline(always)]
394 pub const fn variant(&self) -> Rightlow {
395 match self.bits {
396 false => Rightlow::RightHigh,
397 true => Rightlow::RightLow,
398 }
399 }
400 #[doc = "The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel."]
401 #[inline(always)]
402 pub fn is_right_high(&self) -> bool {
403 *self == Rightlow::RightHigh
404 }
405 #[doc = "The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel."]
406 #[inline(always)]
407 pub fn is_right_low(&self) -> bool {
408 *self == Rightlow::RightLow
409 }
410}
411#[doc = "Field `RIGHTLOW` writer - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed."]
412pub type RightlowW<'a, REG> = crate::BitWriter<'a, REG, Rightlow>;
413impl<'a, REG> RightlowW<'a, REG>
414where
415 REG: crate::Writable + crate::RegisterSpec,
416{
417 #[doc = "The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel."]
418 #[inline(always)]
419 pub fn right_high(self) -> &'a mut crate::W<REG> {
420 self.variant(Rightlow::RightHigh)
421 }
422 #[doc = "The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel."]
423 #[inline(always)]
424 pub fn right_low(self) -> &'a mut crate::W<REG> {
425 self.variant(Rightlow::RightLow)
426 }
427}
428#[doc = "Left Justify data.\n\nValue on reset: 0"]
429#[cfg_attr(feature = "defmt", derive(defmt::Format))]
430#[derive(Clone, Copy, Debug, PartialEq, Eq)]
431pub enum Leftjust {
432 #[doc = "0: Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus."]
433 RightJustified = 0,
434 #[doc = "1: Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus."]
435 LeftJustified = 1,
436}
437impl From<Leftjust> for bool {
438 #[inline(always)]
439 fn from(variant: Leftjust) -> Self {
440 variant as u8 != 0
441 }
442}
443#[doc = "Field `LEFTJUST` reader - Left Justify data."]
444pub type LeftjustR = crate::BitReader<Leftjust>;
445impl LeftjustR {
446 #[doc = "Get enumerated values variant"]
447 #[inline(always)]
448 pub const fn variant(&self) -> Leftjust {
449 match self.bits {
450 false => Leftjust::RightJustified,
451 true => Leftjust::LeftJustified,
452 }
453 }
454 #[doc = "Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus."]
455 #[inline(always)]
456 pub fn is_right_justified(&self) -> bool {
457 *self == Leftjust::RightJustified
458 }
459 #[doc = "Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus."]
460 #[inline(always)]
461 pub fn is_left_justified(&self) -> bool {
462 *self == Leftjust::LeftJustified
463 }
464}
465#[doc = "Field `LEFTJUST` writer - Left Justify data."]
466pub type LeftjustW<'a, REG> = crate::BitWriter<'a, REG, Leftjust>;
467impl<'a, REG> LeftjustW<'a, REG>
468where
469 REG: crate::Writable + crate::RegisterSpec,
470{
471 #[doc = "Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus."]
472 #[inline(always)]
473 pub fn right_justified(self) -> &'a mut crate::W<REG> {
474 self.variant(Leftjust::RightJustified)
475 }
476 #[doc = "Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus."]
477 #[inline(always)]
478 pub fn left_justified(self) -> &'a mut crate::W<REG> {
479 self.variant(Leftjust::LeftJustified)
480 }
481}
482#[doc = "Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers.\n\nValue on reset: 0"]
483#[cfg_attr(feature = "defmt", derive(defmt::Format))]
484#[derive(Clone, Copy, Debug, PartialEq, Eq)]
485pub enum Onechannel {
486 #[doc = "0: I2S data for this channel pair is treated as left and right channels."]
487 DualChannel = 0,
488 #[doc = "1: I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION."]
489 SingleChannel = 1,
490}
491impl From<Onechannel> for bool {
492 #[inline(always)]
493 fn from(variant: Onechannel) -> Self {
494 variant as u8 != 0
495 }
496}
497#[doc = "Field `ONECHANNEL` reader - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers."]
498pub type OnechannelR = crate::BitReader<Onechannel>;
499impl OnechannelR {
500 #[doc = "Get enumerated values variant"]
501 #[inline(always)]
502 pub const fn variant(&self) -> Onechannel {
503 match self.bits {
504 false => Onechannel::DualChannel,
505 true => Onechannel::SingleChannel,
506 }
507 }
508 #[doc = "I2S data for this channel pair is treated as left and right channels."]
509 #[inline(always)]
510 pub fn is_dual_channel(&self) -> bool {
511 *self == Onechannel::DualChannel
512 }
513 #[doc = "I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION."]
514 #[inline(always)]
515 pub fn is_single_channel(&self) -> bool {
516 *self == Onechannel::SingleChannel
517 }
518}
519#[doc = "Field `ONECHANNEL` writer - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers."]
520pub type OnechannelW<'a, REG> = crate::BitWriter<'a, REG, Onechannel>;
521impl<'a, REG> OnechannelW<'a, REG>
522where
523 REG: crate::Writable + crate::RegisterSpec,
524{
525 #[doc = "I2S data for this channel pair is treated as left and right channels."]
526 #[inline(always)]
527 pub fn dual_channel(self) -> &'a mut crate::W<REG> {
528 self.variant(Onechannel::DualChannel)
529 }
530 #[doc = "I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION."]
531 #[inline(always)]
532 pub fn single_channel(self) -> &'a mut crate::W<REG> {
533 self.variant(Onechannel::SingleChannel)
534 }
535}
536#[doc = "PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7.\n\nValue on reset: 0"]
537#[cfg_attr(feature = "defmt", derive(defmt::Format))]
538#[derive(Clone, Copy, Debug, PartialEq, Eq)]
539pub enum Pdmdata {
540 #[doc = "0: Normal operation, data is transferred to or from the Flexcomm FIFO."]
541 Normal = 0,
542 #[doc = "1: The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun."]
543 DmicSubsystem = 1,
544}
545impl From<Pdmdata> for bool {
546 #[inline(always)]
547 fn from(variant: Pdmdata) -> Self {
548 variant as u8 != 0
549 }
550}
551#[doc = "Field `PDMDATA` reader - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7."]
552pub type PdmdataR = crate::BitReader<Pdmdata>;
553impl PdmdataR {
554 #[doc = "Get enumerated values variant"]
555 #[inline(always)]
556 pub const fn variant(&self) -> Pdmdata {
557 match self.bits {
558 false => Pdmdata::Normal,
559 true => Pdmdata::DmicSubsystem,
560 }
561 }
562 #[doc = "Normal operation, data is transferred to or from the Flexcomm FIFO."]
563 #[inline(always)]
564 pub fn is_normal(&self) -> bool {
565 *self == Pdmdata::Normal
566 }
567 #[doc = "The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun."]
568 #[inline(always)]
569 pub fn is_dmic_subsystem(&self) -> bool {
570 *self == Pdmdata::DmicSubsystem
571 }
572}
573#[doc = "Field `PDMDATA` writer - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7."]
574pub type PdmdataW<'a, REG> = crate::BitWriter<'a, REG, Pdmdata>;
575impl<'a, REG> PdmdataW<'a, REG>
576where
577 REG: crate::Writable + crate::RegisterSpec,
578{
579 #[doc = "Normal operation, data is transferred to or from the Flexcomm FIFO."]
580 #[inline(always)]
581 pub fn normal(self) -> &'a mut crate::W<REG> {
582 self.variant(Pdmdata::Normal)
583 }
584 #[doc = "The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun."]
585 #[inline(always)]
586 pub fn dmic_subsystem(self) -> &'a mut crate::W<REG> {
587 self.variant(Pdmdata::DmicSubsystem)
588 }
589}
590#[doc = "SCK polarity.\n\nValue on reset: 0"]
591#[cfg_attr(feature = "defmt", derive(defmt::Format))]
592#[derive(Clone, Copy, Debug, PartialEq, Eq)]
593pub enum SckPol {
594 #[doc = "0: Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S)."]
595 FallingEdge = 0,
596 #[doc = "1: Data is launched on SCK rising edges and sampled on SCK falling edges."]
597 RisingEdge = 1,
598}
599impl From<SckPol> for bool {
600 #[inline(always)]
601 fn from(variant: SckPol) -> Self {
602 variant as u8 != 0
603 }
604}
605#[doc = "Field `SCK_POL` reader - SCK polarity."]
606pub type SckPolR = crate::BitReader<SckPol>;
607impl SckPolR {
608 #[doc = "Get enumerated values variant"]
609 #[inline(always)]
610 pub const fn variant(&self) -> SckPol {
611 match self.bits {
612 false => SckPol::FallingEdge,
613 true => SckPol::RisingEdge,
614 }
615 }
616 #[doc = "Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S)."]
617 #[inline(always)]
618 pub fn is_falling_edge(&self) -> bool {
619 *self == SckPol::FallingEdge
620 }
621 #[doc = "Data is launched on SCK rising edges and sampled on SCK falling edges."]
622 #[inline(always)]
623 pub fn is_rising_edge(&self) -> bool {
624 *self == SckPol::RisingEdge
625 }
626}
627#[doc = "Field `SCK_POL` writer - SCK polarity."]
628pub type SckPolW<'a, REG> = crate::BitWriter<'a, REG, SckPol>;
629impl<'a, REG> SckPolW<'a, REG>
630where
631 REG: crate::Writable + crate::RegisterSpec,
632{
633 #[doc = "Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S)."]
634 #[inline(always)]
635 pub fn falling_edge(self) -> &'a mut crate::W<REG> {
636 self.variant(SckPol::FallingEdge)
637 }
638 #[doc = "Data is launched on SCK rising edges and sampled on SCK falling edges."]
639 #[inline(always)]
640 pub fn rising_edge(self) -> &'a mut crate::W<REG> {
641 self.variant(SckPol::RisingEdge)
642 }
643}
644#[doc = "WS polarity.\n\nValue on reset: 0"]
645#[cfg_attr(feature = "defmt", derive(defmt::Format))]
646#[derive(Clone, Copy, Debug, PartialEq, Eq)]
647pub enum WsPol {
648 #[doc = "0: Data frames begin at a falling edge of WS (standard for classic I2S)."]
649 NotInverted = 0,
650 #[doc = "1: WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S)."]
651 Inverted = 1,
652}
653impl From<WsPol> for bool {
654 #[inline(always)]
655 fn from(variant: WsPol) -> Self {
656 variant as u8 != 0
657 }
658}
659#[doc = "Field `WS_POL` reader - WS polarity."]
660pub type WsPolR = crate::BitReader<WsPol>;
661impl WsPolR {
662 #[doc = "Get enumerated values variant"]
663 #[inline(always)]
664 pub const fn variant(&self) -> WsPol {
665 match self.bits {
666 false => WsPol::NotInverted,
667 true => WsPol::Inverted,
668 }
669 }
670 #[doc = "Data frames begin at a falling edge of WS (standard for classic I2S)."]
671 #[inline(always)]
672 pub fn is_not_inverted(&self) -> bool {
673 *self == WsPol::NotInverted
674 }
675 #[doc = "WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S)."]
676 #[inline(always)]
677 pub fn is_inverted(&self) -> bool {
678 *self == WsPol::Inverted
679 }
680}
681#[doc = "Field `WS_POL` writer - WS polarity."]
682pub type WsPolW<'a, REG> = crate::BitWriter<'a, REG, WsPol>;
683impl<'a, REG> WsPolW<'a, REG>
684where
685 REG: crate::Writable + crate::RegisterSpec,
686{
687 #[doc = "Data frames begin at a falling edge of WS (standard for classic I2S)."]
688 #[inline(always)]
689 pub fn not_inverted(self) -> &'a mut crate::W<REG> {
690 self.variant(WsPol::NotInverted)
691 }
692 #[doc = "WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S)."]
693 #[inline(always)]
694 pub fn inverted(self) -> &'a mut crate::W<REG> {
695 self.variant(WsPol::Inverted)
696 }
697}
698#[doc = "Field `DATALEN` reader - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length"]
699pub type DatalenR = crate::FieldReader;
700#[doc = "Field `DATALEN` writer - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length"]
701pub type DatalenW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
702impl R {
703 #[doc = "Bit 0 - Main enable for I 2S function in this Flexcomm"]
704 #[inline(always)]
705 pub fn mainenable(&self) -> MainenableR {
706 MainenableR::new((self.bits & 1) != 0)
707 }
708 #[doc = "Bit 1 - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame."]
709 #[inline(always)]
710 pub fn datapause(&self) -> DatapauseR {
711 DatapauseR::new(((self.bits >> 1) & 1) != 0)
712 }
713 #[doc = "Bits 2:3 - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm."]
714 #[inline(always)]
715 pub fn paircount(&self) -> PaircountR {
716 PaircountR::new(((self.bits >> 2) & 3) as u8)
717 }
718 #[doc = "Bits 4:5 - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm."]
719 #[inline(always)]
720 pub fn mstslvcfg(&self) -> MstslvcfgR {
721 MstslvcfgR::new(((self.bits >> 4) & 3) as u8)
722 }
723 #[doc = "Bits 6:7 - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples."]
724 #[inline(always)]
725 pub fn mode(&self) -> ModeR {
726 ModeR::new(((self.bits >> 6) & 3) as u8)
727 }
728 #[doc = "Bit 8 - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed."]
729 #[inline(always)]
730 pub fn rightlow(&self) -> RightlowR {
731 RightlowR::new(((self.bits >> 8) & 1) != 0)
732 }
733 #[doc = "Bit 9 - Left Justify data."]
734 #[inline(always)]
735 pub fn leftjust(&self) -> LeftjustR {
736 LeftjustR::new(((self.bits >> 9) & 1) != 0)
737 }
738 #[doc = "Bit 10 - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers."]
739 #[inline(always)]
740 pub fn onechannel(&self) -> OnechannelR {
741 OnechannelR::new(((self.bits >> 10) & 1) != 0)
742 }
743 #[doc = "Bit 11 - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7."]
744 #[inline(always)]
745 pub fn pdmdata(&self) -> PdmdataR {
746 PdmdataR::new(((self.bits >> 11) & 1) != 0)
747 }
748 #[doc = "Bit 12 - SCK polarity."]
749 #[inline(always)]
750 pub fn sck_pol(&self) -> SckPolR {
751 SckPolR::new(((self.bits >> 12) & 1) != 0)
752 }
753 #[doc = "Bit 13 - WS polarity."]
754 #[inline(always)]
755 pub fn ws_pol(&self) -> WsPolR {
756 WsPolR::new(((self.bits >> 13) & 1) != 0)
757 }
758 #[doc = "Bits 16:20 - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length"]
759 #[inline(always)]
760 pub fn datalen(&self) -> DatalenR {
761 DatalenR::new(((self.bits >> 16) & 0x1f) as u8)
762 }
763}
764#[cfg(feature = "debug")]
765impl core::fmt::Debug for R {
766 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
767 f.debug_struct("CFG1")
768 .field("mainenable", &self.mainenable())
769 .field("datapause", &self.datapause())
770 .field("paircount", &self.paircount())
771 .field("mstslvcfg", &self.mstslvcfg())
772 .field("mode", &self.mode())
773 .field("rightlow", &self.rightlow())
774 .field("leftjust", &self.leftjust())
775 .field("onechannel", &self.onechannel())
776 .field("pdmdata", &self.pdmdata())
777 .field("sck_pol", &self.sck_pol())
778 .field("ws_pol", &self.ws_pol())
779 .field("datalen", &self.datalen())
780 .finish()
781 }
782}
783impl W {
784 #[doc = "Bit 0 - Main enable for I 2S function in this Flexcomm"]
785 #[inline(always)]
786 pub fn mainenable(&mut self) -> MainenableW<Cfg1Spec> {
787 MainenableW::new(self, 0)
788 }
789 #[doc = "Bit 1 - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame."]
790 #[inline(always)]
791 pub fn datapause(&mut self) -> DatapauseW<Cfg1Spec> {
792 DatapauseW::new(self, 1)
793 }
794 #[doc = "Bits 2:3 - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm."]
795 #[inline(always)]
796 pub fn paircount(&mut self) -> PaircountW<Cfg1Spec> {
797 PaircountW::new(self, 2)
798 }
799 #[doc = "Bits 4:5 - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm."]
800 #[inline(always)]
801 pub fn mstslvcfg(&mut self) -> MstslvcfgW<Cfg1Spec> {
802 MstslvcfgW::new(self, 4)
803 }
804 #[doc = "Bits 6:7 - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples."]
805 #[inline(always)]
806 pub fn mode(&mut self) -> ModeW<Cfg1Spec> {
807 ModeW::new(self, 6)
808 }
809 #[doc = "Bit 8 - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed."]
810 #[inline(always)]
811 pub fn rightlow(&mut self) -> RightlowW<Cfg1Spec> {
812 RightlowW::new(self, 8)
813 }
814 #[doc = "Bit 9 - Left Justify data."]
815 #[inline(always)]
816 pub fn leftjust(&mut self) -> LeftjustW<Cfg1Spec> {
817 LeftjustW::new(self, 9)
818 }
819 #[doc = "Bit 10 - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers."]
820 #[inline(always)]
821 pub fn onechannel(&mut self) -> OnechannelW<Cfg1Spec> {
822 OnechannelW::new(self, 10)
823 }
824 #[doc = "Bit 11 - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7."]
825 #[inline(always)]
826 pub fn pdmdata(&mut self) -> PdmdataW<Cfg1Spec> {
827 PdmdataW::new(self, 11)
828 }
829 #[doc = "Bit 12 - SCK polarity."]
830 #[inline(always)]
831 pub fn sck_pol(&mut self) -> SckPolW<Cfg1Spec> {
832 SckPolW::new(self, 12)
833 }
834 #[doc = "Bit 13 - WS polarity."]
835 #[inline(always)]
836 pub fn ws_pol(&mut self) -> WsPolW<Cfg1Spec> {
837 WsPolW::new(self, 13)
838 }
839 #[doc = "Bits 16:20 - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the I2S: Determines the size of data transfers between the FIFO and the I2S serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = data is 32 bits in length"]
840 #[inline(always)]
841 pub fn datalen(&mut self) -> DatalenW<Cfg1Spec> {
842 DatalenW::new(self, 16)
843 }
844}
845#[doc = "Configuration register 1 for the primary channel pair.\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
846pub struct Cfg1Spec;
847impl crate::RegisterSpec for Cfg1Spec {
848 type Ux = u32;
849}
850#[doc = "`read()` method returns [`cfg1::R`](R) reader structure"]
851impl crate::Readable for Cfg1Spec {}
852#[doc = "`write(|w| ..)` method takes [`cfg1::W`](W) writer structure"]
853impl crate::Writable for Cfg1Spec {
854 type Safety = crate::Unsafe;
855 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
856 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
857}
858#[doc = "`reset()` method sets CFG1 to value 0"]
859impl crate::Resettable for Cfg1Spec {
860 const RESET_VALUE: u32 = 0;
861}