mimxrt685s_pac/hashcrypt/
memctrl.rs1#[doc = "Register `MEMCTRL` reader"]
2pub type R = crate::R<MemctrlSpec>;
3#[doc = "Register `MEMCTRL` writer"]
4pub type W = crate::W<MemctrlSpec>;
5#[doc = "Enables mastering.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Master {
9 #[doc = "0: Mastering is not used and the normal DMA or Interrupt based model is used with INDATA."]
10 NotUsed = 0,
11 #[doc = "1: Mastering is enabled and DMA and INDATA should not be used."]
12 Enabled = 1,
13}
14impl From<Master> for bool {
15 #[inline(always)]
16 fn from(variant: Master) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `MASTER` reader - Enables mastering."]
21pub type MasterR = crate::BitReader<Master>;
22impl MasterR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> Master {
26 match self.bits {
27 false => Master::NotUsed,
28 true => Master::Enabled,
29 }
30 }
31 #[doc = "Mastering is not used and the normal DMA or Interrupt based model is used with INDATA."]
32 #[inline(always)]
33 pub fn is_not_used(&self) -> bool {
34 *self == Master::NotUsed
35 }
36 #[doc = "Mastering is enabled and DMA and INDATA should not be used."]
37 #[inline(always)]
38 pub fn is_enabled(&self) -> bool {
39 *self == Master::Enabled
40 }
41}
42#[doc = "Field `MASTER` writer - Enables mastering."]
43pub type MasterW<'a, REG> = crate::BitWriter<'a, REG, Master>;
44impl<'a, REG> MasterW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "Mastering is not used and the normal DMA or Interrupt based model is used with INDATA."]
49 #[inline(always)]
50 pub fn not_used(self) -> &'a mut crate::W<REG> {
51 self.variant(Master::NotUsed)
52 }
53 #[doc = "Mastering is enabled and DMA and INDATA should not be used."]
54 #[inline(always)]
55 pub fn enabled(self) -> &'a mut crate::W<REG> {
56 self.variant(Master::Enabled)
57 }
58}
59#[doc = "Field `COUNT` reader - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash."]
60pub type CountR = crate::FieldReader<u16>;
61#[doc = "Field `COUNT` writer - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash."]
62pub type CountW<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
63impl R {
64 #[doc = "Bit 0 - Enables mastering."]
65 #[inline(always)]
66 pub fn master(&self) -> MasterR {
67 MasterR::new((self.bits & 1) != 0)
68 }
69 #[doc = "Bits 16:26 - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash."]
70 #[inline(always)]
71 pub fn count(&self) -> CountR {
72 CountR::new(((self.bits >> 16) & 0x07ff) as u16)
73 }
74}
75#[cfg(feature = "debug")]
76impl core::fmt::Debug for R {
77 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
78 f.debug_struct("MEMCTRL")
79 .field("master", &self.master())
80 .field("count", &self.count())
81 .finish()
82 }
83}
84impl W {
85 #[doc = "Bit 0 - Enables mastering."]
86 #[inline(always)]
87 pub fn master(&mut self) -> MasterW<MemctrlSpec> {
88 MasterW::new(self, 0)
89 }
90 #[doc = "Bits 16:26 - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks to copy starting at MEMADDR. This register will decrement after each block is copied, ending in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA interrupt will occur on ever block. If a bus error occurs, it will stop with this field set to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) blocks to hash."]
91 #[inline(always)]
92 pub fn count(&mut self) -> CountW<MemctrlSpec> {
93 CountW::new(self, 16)
94 }
95}
96#[doc = "Setup Master to access memory (if available)\n\nYou can [`read`](crate::Reg::read) this register and get [`memctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`memctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
97pub struct MemctrlSpec;
98impl crate::RegisterSpec for MemctrlSpec {
99 type Ux = u32;
100}
101#[doc = "`read()` method returns [`memctrl::R`](R) reader structure"]
102impl crate::Readable for MemctrlSpec {}
103#[doc = "`write(|w| ..)` method takes [`memctrl::W`](W) writer structure"]
104impl crate::Writable for MemctrlSpec {
105 type Safety = crate::Unsafe;
106 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
107 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
108}
109#[doc = "`reset()` method sets MEMCTRL to value 0"]
110impl crate::Resettable for MemctrlSpec {
111 const RESET_VALUE: u32 = 0;
112}