mimxrt685s_pac/hashcrypt/
intenclr.rs

1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `WAITING` reader - Write 1 to clear mask."]
6pub type WaitingR = crate::BitReader;
7#[doc = "Field `WAITING` writer - Write 1 to clear mask."]
8pub type WaitingW<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `DIGEST` reader - Write 1 to clear mask."]
10pub type DigestR = crate::BitReader;
11#[doc = "Field `DIGEST` writer - Write 1 to clear mask."]
12pub type DigestW<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `ERROR` reader - Write 1 to clear mask."]
14pub type ErrorR = crate::BitReader;
15#[doc = "Field `ERROR` writer - Write 1 to clear mask."]
16pub type ErrorW<'a, REG> = crate::BitWriter1C<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - Write 1 to clear mask."]
19    #[inline(always)]
20    pub fn waiting(&self) -> WaitingR {
21        WaitingR::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - Write 1 to clear mask."]
24    #[inline(always)]
25    pub fn digest(&self) -> DigestR {
26        DigestR::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 2 - Write 1 to clear mask."]
29    #[inline(always)]
30    pub fn error(&self) -> ErrorR {
31        ErrorR::new(((self.bits >> 2) & 1) != 0)
32    }
33}
34#[cfg(feature = "debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("INTENCLR")
38            .field("waiting", &self.waiting())
39            .field("digest", &self.digest())
40            .field("error", &self.error())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bit 0 - Write 1 to clear mask."]
46    #[inline(always)]
47    pub fn waiting(&mut self) -> WaitingW<IntenclrSpec> {
48        WaitingW::new(self, 0)
49    }
50    #[doc = "Bit 1 - Write 1 to clear mask."]
51    #[inline(always)]
52    pub fn digest(&mut self) -> DigestW<IntenclrSpec> {
53        DigestW::new(self, 1)
54    }
55    #[doc = "Bit 2 - Write 1 to clear mask."]
56    #[inline(always)]
57    pub fn error(&mut self) -> ErrorW<IntenclrSpec> {
58        ErrorW::new(self, 2)
59    }
60}
61#[doc = "Write 1 to clear interrupts.\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct IntenclrSpec;
63impl crate::RegisterSpec for IntenclrSpec {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
67impl crate::Readable for IntenclrSpec {}
68#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
69impl crate::Writable for IntenclrSpec {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x07;
73}
74#[doc = "`reset()` method sets INTENCLR to value 0"]
75impl crate::Resettable for IntenclrSpec {
76    const RESET_VALUE: u32 = 0;
77}
mimxrt685s_pac/hashcrypt/intenclr.rs

mimxrt685s_pac/hashcrypt/
intenclr.rs
