mimxrt685s_pac/gpio/
intpol.rs

1#[doc = "Register `INTPOL[%s]` reader"]
2pub type R = crate::R<IntpolSpec>;
3#[doc = "Register `INTPOL[%s]` writer"]
4pub type W = crate::W<IntpolSpec>;
5#[doc = "polarity control for each pin(bit 0 for pion_0, bit 1 for pion_1, etc.)\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u32)]
9pub enum PolCtl {
10    #[doc = "0: interrupt when gpio high"]
11    Hihg = 0,
12    #[doc = "1: interrupt when gpio low"]
13    Low = 1,
14}
15impl From<PolCtl> for u32 {
16    #[inline(always)]
17    fn from(variant: PolCtl) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for PolCtl {
22    type Ux = u32;
23}
24impl crate::IsEnum for PolCtl {}
25#[doc = "Field `POL_CTL` reader - polarity control for each pin(bit 0 for pion_0, bit 1 for pion_1, etc.)"]
26pub type PolCtlR = crate::FieldReader<PolCtl>;
27impl PolCtlR {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<PolCtl> {
31        match self.bits {
32            0 => Some(PolCtl::Hihg),
33            1 => Some(PolCtl::Low),
34            _ => None,
35        }
36    }
37    #[doc = "interrupt when gpio high"]
38    #[inline(always)]
39    pub fn is_hihg(&self) -> bool {
40        *self == PolCtl::Hihg
41    }
42    #[doc = "interrupt when gpio low"]
43    #[inline(always)]
44    pub fn is_low(&self) -> bool {
45        *self == PolCtl::Low
46    }
47}
48#[doc = "Field `POL_CTL` writer - polarity control for each pin(bit 0 for pion_0, bit 1 for pion_1, etc.)"]
49pub type PolCtlW<'a, REG> = crate::FieldWriter<'a, REG, 32, PolCtl>;
50impl<'a, REG> PolCtlW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53    REG::Ux: From<u32>,
54{
55    #[doc = "interrupt when gpio high"]
56    #[inline(always)]
57    pub fn hihg(self) -> &'a mut crate::W<REG> {
58        self.variant(PolCtl::Hihg)
59    }
60    #[doc = "interrupt when gpio low"]
61    #[inline(always)]
62    pub fn low(self) -> &'a mut crate::W<REG> {
63        self.variant(PolCtl::Low)
64    }
65}
66impl R {
67    #[doc = "Bits 0:31 - polarity control for each pin(bit 0 for pion_0, bit 1 for pion_1, etc.)"]
68    #[inline(always)]
69    pub fn pol_ctl(&self) -> PolCtlR {
70        PolCtlR::new(self.bits)
71    }
72}
73#[cfg(feature = "debug")]
74impl core::fmt::Debug for R {
75    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
76        f.debug_struct("INTPOL")
77            .field("pol_ctl", &self.pol_ctl())
78            .finish()
79    }
80}
81impl W {
82    #[doc = "Bits 0:31 - polarity control for each pin(bit 0 for pion_0, bit 1 for pion_1, etc.)"]
83    #[inline(always)]
84    pub fn pol_ctl(&mut self) -> PolCtlW<IntpolSpec> {
85        PolCtlW::new(self, 0)
86    }
87}
88#[doc = "interupt polarity control register\n\nYou can [`read`](crate::Reg::read) this register and get [`intpol::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intpol::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
89pub struct IntpolSpec;
90impl crate::RegisterSpec for IntpolSpec {
91    type Ux = u32;
92}
93#[doc = "`read()` method returns [`intpol::R`](R) reader structure"]
94impl crate::Readable for IntpolSpec {}
95#[doc = "`write(|w| ..)` method takes [`intpol::W`](W) writer structure"]
96impl crate::Writable for IntpolSpec {
97    type Safety = crate::Unsafe;
98    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
99    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
100}
101#[doc = "`reset()` method sets INTPOL[%s]
102to value 0"]
103impl crate::Resettable for IntpolSpec {
104    const RESET_VALUE: u32 = 0;
105}
mimxrt685s_pac/gpio/intpol.rs

mimxrt685s_pac/gpio/
intpol.rs
