mimxrt685s_pac/gpio/
intedg.rs

1#[doc = "Register `INTEDG[%s]` reader"]
2pub type R = crate::R<IntedgSpec>;
3#[doc = "Register `INTEDG[%s]` writer"]
4pub type W = crate::W<IntedgSpec>;
5#[doc = "choose level or edge based detection for each pin(bit0 for pion_0, bit1 for pion_1, etc)\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u32)]
9pub enum Edge {
10    #[doc = "0: level"]
11    Level = 0,
12    #[doc = "1: edge"]
13    Edge = 1,
14}
15impl From<Edge> for u32 {
16    #[inline(always)]
17    fn from(variant: Edge) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for Edge {
22    type Ux = u32;
23}
24impl crate::IsEnum for Edge {}
25#[doc = "Field `EDGE` reader - choose level or edge based detection for each pin(bit0 for pion_0, bit1 for pion_1, etc)"]
26pub type EdgeR = crate::FieldReader<Edge>;
27impl EdgeR {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<Edge> {
31        match self.bits {
32            0 => Some(Edge::Level),
33            1 => Some(Edge::Edge),
34            _ => None,
35        }
36    }
37    #[doc = "level"]
38    #[inline(always)]
39    pub fn is_level(&self) -> bool {
40        *self == Edge::Level
41    }
42    #[doc = "edge"]
43    #[inline(always)]
44    pub fn is_edge(&self) -> bool {
45        *self == Edge::Edge
46    }
47}
48#[doc = "Field `EDGE` writer - choose level or edge based detection for each pin(bit0 for pion_0, bit1 for pion_1, etc)"]
49pub type EdgeW<'a, REG> = crate::FieldWriter<'a, REG, 32, Edge>;
50impl<'a, REG> EdgeW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53    REG::Ux: From<u32>,
54{
55    #[doc = "level"]
56    #[inline(always)]
57    pub fn level(self) -> &'a mut crate::W<REG> {
58        self.variant(Edge::Level)
59    }
60    #[doc = "edge"]
61    #[inline(always)]
62    pub fn edge(self) -> &'a mut crate::W<REG> {
63        self.variant(Edge::Edge)
64    }
65}
66impl R {
67    #[doc = "Bits 0:31 - choose level or edge based detection for each pin(bit0 for pion_0, bit1 for pion_1, etc)"]
68    #[inline(always)]
69    pub fn edge(&self) -> EdgeR {
70        EdgeR::new(self.bits)
71    }
72}
73#[cfg(feature = "debug")]
74impl core::fmt::Debug for R {
75    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
76        f.debug_struct("INTEDG")
77            .field("edge", &self.edge())
78            .finish()
79    }
80}
81impl W {
82    #[doc = "Bits 0:31 - choose level or edge based detection for each pin(bit0 for pion_0, bit1 for pion_1, etc)"]
83    #[inline(always)]
84    pub fn edge(&mut self) -> EdgeW<IntedgSpec> {
85        EdgeW::new(self, 0)
86    }
87}
88#[doc = "choose edge or level for interrupt\n\nYou can [`read`](crate::Reg::read) this register and get [`intedg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intedg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
89pub struct IntedgSpec;
90impl crate::RegisterSpec for IntedgSpec {
91    type Ux = u32;
92}
93#[doc = "`read()` method returns [`intedg::R`](R) reader structure"]
94impl crate::Readable for IntedgSpec {}
95#[doc = "`write(|w| ..)` method takes [`intedg::W`](W) writer structure"]
96impl crate::Writable for IntedgSpec {
97    type Safety = crate::Unsafe;
98    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
99    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
100}
101#[doc = "`reset()` method sets INTEDG[%s]
102to value 0"]
103impl crate::Resettable for IntedgSpec {
104    const RESET_VALUE: u32 = 0;
105}
mimxrt685s_pac/gpio/intedg.rs

mimxrt685s_pac/gpio/
intedg.rs
