mimxrt685s_pac/flexspi/
intr.rs1#[doc = "Register `INTR` reader"]
2pub type R = crate::R<IntrSpec>;
3#[doc = "Register `INTR` writer"]
4pub type W = crate::W<IntrSpec>;
5#[doc = "Field `IPCMDDONE` reader - IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated."]
6pub type IpcmddoneR = crate::BitReader;
7#[doc = "Field `IPCMDDONE` writer - IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated."]
8pub type IpcmddoneW<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `IPCMDGE` reader - IP triggered Command Sequences Grant Timeout interrupt."]
10pub type IpcmdgeR = crate::BitReader;
11#[doc = "Field `IPCMDGE` writer - IP triggered Command Sequences Grant Timeout interrupt."]
12pub type IpcmdgeW<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `AHBCMDGE` reader - AHB triggered Command Sequences Grant Timeout interrupt."]
14pub type AhbcmdgeR = crate::BitReader;
15#[doc = "Field `AHBCMDGE` writer - AHB triggered Command Sequences Grant Timeout interrupt."]
16pub type AhbcmdgeW<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `IPCMDERR` reader - IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all."]
18pub type IpcmderrR = crate::BitReader;
19#[doc = "Field `IPCMDERR` writer - IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all."]
20pub type IpcmderrW<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `AHBCMDERR` reader - AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all."]
22pub type AhbcmderrR = crate::BitReader;
23#[doc = "Field `AHBCMDERR` writer - AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all."]
24pub type AhbcmderrW<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `IPRXWA` reader - IP RX FIFO watermark available interrupt."]
26pub type IprxwaR = crate::BitReader;
27#[doc = "Field `IPRXWA` writer - IP RX FIFO watermark available interrupt."]
28pub type IprxwaW<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `IPTXWE` reader - IP TX FIFO watermark empty interrupt."]
30pub type IptxweR = crate::BitReader;
31#[doc = "Field `IPTXWE` writer - IP TX FIFO watermark empty interrupt."]
32pub type IptxweW<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `DATALEARNFAIL` reader - Data Learning failed interrupt."]
34pub type DatalearnfailR = crate::BitReader;
35#[doc = "Field `DATALEARNFAIL` writer - Data Learning failed interrupt."]
36pub type DatalearnfailW<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `SCKSTOPBYRD` reader - SCLK is stopped during command sequence because Async RX FIFO full interrupt."]
38pub type SckstopbyrdR = crate::BitReader;
39#[doc = "Field `SCKSTOPBYRD` writer - SCLK is stopped during command sequence because Async RX FIFO full interrupt."]
40pub type SckstopbyrdW<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[doc = "Field `SCKSTOPBYWR` reader - SCLK is stopped during command sequence because Async TX FIFO empty interrupt."]
42pub type SckstopbywrR = crate::BitReader;
43#[doc = "Field `SCKSTOPBYWR` writer - SCLK is stopped during command sequence because Async TX FIFO empty interrupt."]
44pub type SckstopbywrW<'a, REG> = crate::BitWriter1C<'a, REG>;
45#[doc = "Field `AHBBUSTIMEOUT` reader - AHB Bus timeout interrupt.Refer Interrupts chapter for more details."]
46pub type AhbbustimeoutR = crate::BitReader;
47#[doc = "Field `AHBBUSTIMEOUT` writer - AHB Bus timeout interrupt.Refer Interrupts chapter for more details."]
48pub type AhbbustimeoutW<'a, REG> = crate::BitWriter1C<'a, REG>;
49#[doc = "Field `SEQTIMEOUT` reader - Sequence execution timeout interrupt."]
50pub type SeqtimeoutR = crate::BitReader;
51#[doc = "Field `SEQTIMEOUT` writer - Sequence execution timeout interrupt."]
52pub type SeqtimeoutW<'a, REG> = crate::BitWriter1C<'a, REG>;
53impl R {
54 #[doc = "Bit 0 - IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated."]
55 #[inline(always)]
56 pub fn ipcmddone(&self) -> IpcmddoneR {
57 IpcmddoneR::new((self.bits & 1) != 0)
58 }
59 #[doc = "Bit 1 - IP triggered Command Sequences Grant Timeout interrupt."]
60 #[inline(always)]
61 pub fn ipcmdge(&self) -> IpcmdgeR {
62 IpcmdgeR::new(((self.bits >> 1) & 1) != 0)
63 }
64 #[doc = "Bit 2 - AHB triggered Command Sequences Grant Timeout interrupt."]
65 #[inline(always)]
66 pub fn ahbcmdge(&self) -> AhbcmdgeR {
67 AhbcmdgeR::new(((self.bits >> 2) & 1) != 0)
68 }
69 #[doc = "Bit 3 - IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all."]
70 #[inline(always)]
71 pub fn ipcmderr(&self) -> IpcmderrR {
72 IpcmderrR::new(((self.bits >> 3) & 1) != 0)
73 }
74 #[doc = "Bit 4 - AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all."]
75 #[inline(always)]
76 pub fn ahbcmderr(&self) -> AhbcmderrR {
77 AhbcmderrR::new(((self.bits >> 4) & 1) != 0)
78 }
79 #[doc = "Bit 5 - IP RX FIFO watermark available interrupt."]
80 #[inline(always)]
81 pub fn iprxwa(&self) -> IprxwaR {
82 IprxwaR::new(((self.bits >> 5) & 1) != 0)
83 }
84 #[doc = "Bit 6 - IP TX FIFO watermark empty interrupt."]
85 #[inline(always)]
86 pub fn iptxwe(&self) -> IptxweR {
87 IptxweR::new(((self.bits >> 6) & 1) != 0)
88 }
89 #[doc = "Bit 7 - Data Learning failed interrupt."]
90 #[inline(always)]
91 pub fn datalearnfail(&self) -> DatalearnfailR {
92 DatalearnfailR::new(((self.bits >> 7) & 1) != 0)
93 }
94 #[doc = "Bit 8 - SCLK is stopped during command sequence because Async RX FIFO full interrupt."]
95 #[inline(always)]
96 pub fn sckstopbyrd(&self) -> SckstopbyrdR {
97 SckstopbyrdR::new(((self.bits >> 8) & 1) != 0)
98 }
99 #[doc = "Bit 9 - SCLK is stopped during command sequence because Async TX FIFO empty interrupt."]
100 #[inline(always)]
101 pub fn sckstopbywr(&self) -> SckstopbywrR {
102 SckstopbywrR::new(((self.bits >> 9) & 1) != 0)
103 }
104 #[doc = "Bit 10 - AHB Bus timeout interrupt.Refer Interrupts chapter for more details."]
105 #[inline(always)]
106 pub fn ahbbustimeout(&self) -> AhbbustimeoutR {
107 AhbbustimeoutR::new(((self.bits >> 10) & 1) != 0)
108 }
109 #[doc = "Bit 11 - Sequence execution timeout interrupt."]
110 #[inline(always)]
111 pub fn seqtimeout(&self) -> SeqtimeoutR {
112 SeqtimeoutR::new(((self.bits >> 11) & 1) != 0)
113 }
114}
115#[cfg(feature = "debug")]
116impl core::fmt::Debug for R {
117 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
118 f.debug_struct("INTR")
119 .field("ipcmddone", &self.ipcmddone())
120 .field("ipcmdge", &self.ipcmdge())
121 .field("ahbcmdge", &self.ahbcmdge())
122 .field("ipcmderr", &self.ipcmderr())
123 .field("ahbcmderr", &self.ahbcmderr())
124 .field("iprxwa", &self.iprxwa())
125 .field("iptxwe", &self.iptxwe())
126 .field("datalearnfail", &self.datalearnfail())
127 .field("sckstopbyrd", &self.sckstopbyrd())
128 .field("sckstopbywr", &self.sckstopbywr())
129 .field("ahbbustimeout", &self.ahbbustimeout())
130 .field("seqtimeout", &self.seqtimeout())
131 .finish()
132 }
133}
134impl W {
135 #[doc = "Bit 0 - IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated."]
136 #[inline(always)]
137 pub fn ipcmddone(&mut self) -> IpcmddoneW<IntrSpec> {
138 IpcmddoneW::new(self, 0)
139 }
140 #[doc = "Bit 1 - IP triggered Command Sequences Grant Timeout interrupt."]
141 #[inline(always)]
142 pub fn ipcmdge(&mut self) -> IpcmdgeW<IntrSpec> {
143 IpcmdgeW::new(self, 1)
144 }
145 #[doc = "Bit 2 - AHB triggered Command Sequences Grant Timeout interrupt."]
146 #[inline(always)]
147 pub fn ahbcmdge(&mut self) -> AhbcmdgeW<IntrSpec> {
148 AhbcmdgeW::new(self, 2)
149 }
150 #[doc = "Bit 3 - IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all."]
151 #[inline(always)]
152 pub fn ipcmderr(&mut self) -> IpcmderrW<IntrSpec> {
153 IpcmderrW::new(self, 3)
154 }
155 #[doc = "Bit 4 - AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all."]
156 #[inline(always)]
157 pub fn ahbcmderr(&mut self) -> AhbcmderrW<IntrSpec> {
158 AhbcmderrW::new(self, 4)
159 }
160 #[doc = "Bit 5 - IP RX FIFO watermark available interrupt."]
161 #[inline(always)]
162 pub fn iprxwa(&mut self) -> IprxwaW<IntrSpec> {
163 IprxwaW::new(self, 5)
164 }
165 #[doc = "Bit 6 - IP TX FIFO watermark empty interrupt."]
166 #[inline(always)]
167 pub fn iptxwe(&mut self) -> IptxweW<IntrSpec> {
168 IptxweW::new(self, 6)
169 }
170 #[doc = "Bit 7 - Data Learning failed interrupt."]
171 #[inline(always)]
172 pub fn datalearnfail(&mut self) -> DatalearnfailW<IntrSpec> {
173 DatalearnfailW::new(self, 7)
174 }
175 #[doc = "Bit 8 - SCLK is stopped during command sequence because Async RX FIFO full interrupt."]
176 #[inline(always)]
177 pub fn sckstopbyrd(&mut self) -> SckstopbyrdW<IntrSpec> {
178 SckstopbyrdW::new(self, 8)
179 }
180 #[doc = "Bit 9 - SCLK is stopped during command sequence because Async TX FIFO empty interrupt."]
181 #[inline(always)]
182 pub fn sckstopbywr(&mut self) -> SckstopbywrW<IntrSpec> {
183 SckstopbywrW::new(self, 9)
184 }
185 #[doc = "Bit 10 - AHB Bus timeout interrupt.Refer Interrupts chapter for more details."]
186 #[inline(always)]
187 pub fn ahbbustimeout(&mut self) -> AhbbustimeoutW<IntrSpec> {
188 AhbbustimeoutW::new(self, 10)
189 }
190 #[doc = "Bit 11 - Sequence execution timeout interrupt."]
191 #[inline(always)]
192 pub fn seqtimeout(&mut self) -> SeqtimeoutW<IntrSpec> {
193 SeqtimeoutW::new(self, 11)
194 }
195}
196#[doc = "Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`intr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
197pub struct IntrSpec;
198impl crate::RegisterSpec for IntrSpec {
199 type Ux = u32;
200}
201#[doc = "`read()` method returns [`intr::R`](R) reader structure"]
202impl crate::Readable for IntrSpec {}
203#[doc = "`write(|w| ..)` method takes [`intr::W`](W) writer structure"]
204impl crate::Writable for IntrSpec {
205 type Safety = crate::Unsafe;
206 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
207 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0fff;
208}
209#[doc = "`reset()` method sets INTR to value 0"]
210impl crate::Resettable for IntrSpec {
211 const RESET_VALUE: u32 = 0;
212}