mimxrt685s_pac/flexspi/
inten.rs1#[doc = "Register `INTEN` reader"]
2pub type R = crate::R<IntenSpec>;
3#[doc = "Register `INTEN` writer"]
4pub type W = crate::W<IntenSpec>;
5#[doc = "Field `IPCMDDONEEN` reader - IP triggered Command Sequences Execution finished interrupt enable."]
6pub type IpcmddoneenR = crate::BitReader;
7#[doc = "Field `IPCMDDONEEN` writer - IP triggered Command Sequences Execution finished interrupt enable."]
8pub type IpcmddoneenW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IPCMDGEEN` reader - IP triggered Command Sequences Grant Timeout interrupt enable."]
10pub type IpcmdgeenR = crate::BitReader;
11#[doc = "Field `IPCMDGEEN` writer - IP triggered Command Sequences Grant Timeout interrupt enable."]
12pub type IpcmdgeenW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `AHBCMDGEEN` reader - AHB triggered Command Sequences Grant Timeout interrupt enable."]
14pub type AhbcmdgeenR = crate::BitReader;
15#[doc = "Field `AHBCMDGEEN` writer - AHB triggered Command Sequences Grant Timeout interrupt enable."]
16pub type AhbcmdgeenW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `IPCMDERREN` reader - IP triggered Command Sequences Error Detected interrupt enable."]
18pub type IpcmderrenR = crate::BitReader;
19#[doc = "Field `IPCMDERREN` writer - IP triggered Command Sequences Error Detected interrupt enable."]
20pub type IpcmderrenW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `AHBCMDERREN` reader - AHB triggered Command Sequences Error Detected interrupt enable."]
22pub type AhbcmderrenR = crate::BitReader;
23#[doc = "Field `AHBCMDERREN` writer - AHB triggered Command Sequences Error Detected interrupt enable."]
24pub type AhbcmderrenW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `IPRXWAEN` reader - IP RX FIFO WaterMark available interrupt enable."]
26pub type IprxwaenR = crate::BitReader;
27#[doc = "Field `IPRXWAEN` writer - IP RX FIFO WaterMark available interrupt enable."]
28pub type IprxwaenW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `IPTXWEEN` reader - IP TX FIFO WaterMark empty interrupt enable."]
30pub type IptxweenR = crate::BitReader;
31#[doc = "Field `IPTXWEEN` writer - IP TX FIFO WaterMark empty interrupt enable."]
32pub type IptxweenW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DATALEARNFAILEN` reader - Data Learning failed interrupt enable."]
34pub type DatalearnfailenR = crate::BitReader;
35#[doc = "Field `DATALEARNFAILEN` writer - Data Learning failed interrupt enable."]
36pub type DatalearnfailenW<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `SCKSTOPBYRDEN` reader - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable."]
38pub type SckstopbyrdenR = crate::BitReader;
39#[doc = "Field `SCKSTOPBYRDEN` writer - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable."]
40pub type SckstopbyrdenW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SCKSTOPBYWREN` reader - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable."]
42pub type SckstopbywrenR = crate::BitReader;
43#[doc = "Field `SCKSTOPBYWREN` writer - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable."]
44pub type SckstopbywrenW<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `AHBBUSTIMEOUTEN` reader - AHB Bus timeout interrupt.Refer Interrupts chapter for more details."]
46pub type AhbbustimeoutenR = crate::BitReader;
47#[doc = "Field `AHBBUSTIMEOUTEN` writer - AHB Bus timeout interrupt.Refer Interrupts chapter for more details."]
48pub type AhbbustimeoutenW<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `SEQTIMEOUTEN` reader - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details."]
50pub type SeqtimeoutenR = crate::BitReader;
51#[doc = "Field `SEQTIMEOUTEN` writer - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details."]
52pub type SeqtimeoutenW<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54 #[doc = "Bit 0 - IP triggered Command Sequences Execution finished interrupt enable."]
55 #[inline(always)]
56 pub fn ipcmddoneen(&self) -> IpcmddoneenR {
57 IpcmddoneenR::new((self.bits & 1) != 0)
58 }
59 #[doc = "Bit 1 - IP triggered Command Sequences Grant Timeout interrupt enable."]
60 #[inline(always)]
61 pub fn ipcmdgeen(&self) -> IpcmdgeenR {
62 IpcmdgeenR::new(((self.bits >> 1) & 1) != 0)
63 }
64 #[doc = "Bit 2 - AHB triggered Command Sequences Grant Timeout interrupt enable."]
65 #[inline(always)]
66 pub fn ahbcmdgeen(&self) -> AhbcmdgeenR {
67 AhbcmdgeenR::new(((self.bits >> 2) & 1) != 0)
68 }
69 #[doc = "Bit 3 - IP triggered Command Sequences Error Detected interrupt enable."]
70 #[inline(always)]
71 pub fn ipcmderren(&self) -> IpcmderrenR {
72 IpcmderrenR::new(((self.bits >> 3) & 1) != 0)
73 }
74 #[doc = "Bit 4 - AHB triggered Command Sequences Error Detected interrupt enable."]
75 #[inline(always)]
76 pub fn ahbcmderren(&self) -> AhbcmderrenR {
77 AhbcmderrenR::new(((self.bits >> 4) & 1) != 0)
78 }
79 #[doc = "Bit 5 - IP RX FIFO WaterMark available interrupt enable."]
80 #[inline(always)]
81 pub fn iprxwaen(&self) -> IprxwaenR {
82 IprxwaenR::new(((self.bits >> 5) & 1) != 0)
83 }
84 #[doc = "Bit 6 - IP TX FIFO WaterMark empty interrupt enable."]
85 #[inline(always)]
86 pub fn iptxween(&self) -> IptxweenR {
87 IptxweenR::new(((self.bits >> 6) & 1) != 0)
88 }
89 #[doc = "Bit 7 - Data Learning failed interrupt enable."]
90 #[inline(always)]
91 pub fn datalearnfailen(&self) -> DatalearnfailenR {
92 DatalearnfailenR::new(((self.bits >> 7) & 1) != 0)
93 }
94 #[doc = "Bit 8 - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable."]
95 #[inline(always)]
96 pub fn sckstopbyrden(&self) -> SckstopbyrdenR {
97 SckstopbyrdenR::new(((self.bits >> 8) & 1) != 0)
98 }
99 #[doc = "Bit 9 - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable."]
100 #[inline(always)]
101 pub fn sckstopbywren(&self) -> SckstopbywrenR {
102 SckstopbywrenR::new(((self.bits >> 9) & 1) != 0)
103 }
104 #[doc = "Bit 10 - AHB Bus timeout interrupt.Refer Interrupts chapter for more details."]
105 #[inline(always)]
106 pub fn ahbbustimeouten(&self) -> AhbbustimeoutenR {
107 AhbbustimeoutenR::new(((self.bits >> 10) & 1) != 0)
108 }
109 #[doc = "Bit 11 - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details."]
110 #[inline(always)]
111 pub fn seqtimeouten(&self) -> SeqtimeoutenR {
112 SeqtimeoutenR::new(((self.bits >> 11) & 1) != 0)
113 }
114}
115#[cfg(feature = "debug")]
116impl core::fmt::Debug for R {
117 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
118 f.debug_struct("INTEN")
119 .field("ipcmddoneen", &self.ipcmddoneen())
120 .field("ipcmdgeen", &self.ipcmdgeen())
121 .field("ahbcmdgeen", &self.ahbcmdgeen())
122 .field("ipcmderren", &self.ipcmderren())
123 .field("ahbcmderren", &self.ahbcmderren())
124 .field("iprxwaen", &self.iprxwaen())
125 .field("iptxween", &self.iptxween())
126 .field("datalearnfailen", &self.datalearnfailen())
127 .field("sckstopbyrden", &self.sckstopbyrden())
128 .field("sckstopbywren", &self.sckstopbywren())
129 .field("ahbbustimeouten", &self.ahbbustimeouten())
130 .field("seqtimeouten", &self.seqtimeouten())
131 .finish()
132 }
133}
134impl W {
135 #[doc = "Bit 0 - IP triggered Command Sequences Execution finished interrupt enable."]
136 #[inline(always)]
137 pub fn ipcmddoneen(&mut self) -> IpcmddoneenW<IntenSpec> {
138 IpcmddoneenW::new(self, 0)
139 }
140 #[doc = "Bit 1 - IP triggered Command Sequences Grant Timeout interrupt enable."]
141 #[inline(always)]
142 pub fn ipcmdgeen(&mut self) -> IpcmdgeenW<IntenSpec> {
143 IpcmdgeenW::new(self, 1)
144 }
145 #[doc = "Bit 2 - AHB triggered Command Sequences Grant Timeout interrupt enable."]
146 #[inline(always)]
147 pub fn ahbcmdgeen(&mut self) -> AhbcmdgeenW<IntenSpec> {
148 AhbcmdgeenW::new(self, 2)
149 }
150 #[doc = "Bit 3 - IP triggered Command Sequences Error Detected interrupt enable."]
151 #[inline(always)]
152 pub fn ipcmderren(&mut self) -> IpcmderrenW<IntenSpec> {
153 IpcmderrenW::new(self, 3)
154 }
155 #[doc = "Bit 4 - AHB triggered Command Sequences Error Detected interrupt enable."]
156 #[inline(always)]
157 pub fn ahbcmderren(&mut self) -> AhbcmderrenW<IntenSpec> {
158 AhbcmderrenW::new(self, 4)
159 }
160 #[doc = "Bit 5 - IP RX FIFO WaterMark available interrupt enable."]
161 #[inline(always)]
162 pub fn iprxwaen(&mut self) -> IprxwaenW<IntenSpec> {
163 IprxwaenW::new(self, 5)
164 }
165 #[doc = "Bit 6 - IP TX FIFO WaterMark empty interrupt enable."]
166 #[inline(always)]
167 pub fn iptxween(&mut self) -> IptxweenW<IntenSpec> {
168 IptxweenW::new(self, 6)
169 }
170 #[doc = "Bit 7 - Data Learning failed interrupt enable."]
171 #[inline(always)]
172 pub fn datalearnfailen(&mut self) -> DatalearnfailenW<IntenSpec> {
173 DatalearnfailenW::new(self, 7)
174 }
175 #[doc = "Bit 8 - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable."]
176 #[inline(always)]
177 pub fn sckstopbyrden(&mut self) -> SckstopbyrdenW<IntenSpec> {
178 SckstopbyrdenW::new(self, 8)
179 }
180 #[doc = "Bit 9 - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable."]
181 #[inline(always)]
182 pub fn sckstopbywren(&mut self) -> SckstopbywrenW<IntenSpec> {
183 SckstopbywrenW::new(self, 9)
184 }
185 #[doc = "Bit 10 - AHB Bus timeout interrupt.Refer Interrupts chapter for more details."]
186 #[inline(always)]
187 pub fn ahbbustimeouten(&mut self) -> AhbbustimeoutenW<IntenSpec> {
188 AhbbustimeoutenW::new(self, 10)
189 }
190 #[doc = "Bit 11 - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details."]
191 #[inline(always)]
192 pub fn seqtimeouten(&mut self) -> SeqtimeoutenW<IntenSpec> {
193 SeqtimeoutenW::new(self, 11)
194 }
195}
196#[doc = "Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
197pub struct IntenSpec;
198impl crate::RegisterSpec for IntenSpec {
199 type Ux = u32;
200}
201#[doc = "`read()` method returns [`inten::R`](R) reader structure"]
202impl crate::Readable for IntenSpec {}
203#[doc = "`write(|w| ..)` method takes [`inten::W`](W) writer structure"]
204impl crate::Writable for IntenSpec {
205 type Safety = crate::Unsafe;
206 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
207 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
208}
209#[doc = "`reset()` method sets INTEN to value 0"]
210impl crate::Resettable for IntenSpec {
211 const RESET_VALUE: u32 = 0;
212}