mimxrt685s_pac/dma0/
settrig1.rs

1#[doc = "Register `SETTRIG1` writer"]
2pub type W = crate::W<Settrig1Spec>;
3#[doc = "Set Trigger control bit for DMA channel 32.\n\nValue on reset: 0"]
4#[cfg_attr(feature = "defmt", derive(defmt::Format))]
5#[derive(Clone, Copy, Debug, PartialEq, Eq)]
6pub enum Settrig32 {
7    #[doc = "0: No effect."]
8    NoEffect = 0,
9    #[doc = "1: Sets the Trig bit for DMA channel 32."]
10    Effect = 1,
11}
12impl From<Settrig32> for bool {
13    #[inline(always)]
14    fn from(variant: Settrig32) -> Self {
15        variant as u8 != 0
16    }
17}
18#[doc = "Field `SETTRIG32` writer - Set Trigger control bit for DMA channel 32."]
19pub type Settrig32W<'a, REG> = crate::BitWriter<'a, REG, Settrig32>;
20impl<'a, REG> Settrig32W<'a, REG>
21where
22    REG: crate::Writable + crate::RegisterSpec,
23{
24    #[doc = "No effect."]
25    #[inline(always)]
26    pub fn no_effect(self) -> &'a mut crate::W<REG> {
27        self.variant(Settrig32::NoEffect)
28    }
29    #[doc = "Sets the Trig bit for DMA channel 32."]
30    #[inline(always)]
31    pub fn effect(self) -> &'a mut crate::W<REG> {
32        self.variant(Settrig32::Effect)
33    }
34}
35#[doc = "Additional Set Trigger control bits for remaining DMA channels in the range 63 to 33. Any bits above the actually implemented channels are reserved.\n\nValue on reset: 0"]
36#[cfg_attr(feature = "defmt", derive(defmt::Format))]
37#[derive(Clone, Copy, Debug, PartialEq, Eq)]
38#[repr(u32)]
39pub enum Settrig63_33 {
40    #[doc = "0: No effect."]
41    NoEffect = 0,
42    #[doc = "1: Sets the Trig bit for DMA channel for the relevant DMA channel."]
43    Effect = 1,
44}
45impl From<Settrig63_33> for u32 {
46    #[inline(always)]
47    fn from(variant: Settrig63_33) -> Self {
48        variant as _
49    }
50}
51impl crate::FieldSpec for Settrig63_33 {
52    type Ux = u32;
53}
54impl crate::IsEnum for Settrig63_33 {}
55#[doc = "Field `SETTRIG63_33` writer - Additional Set Trigger control bits for remaining DMA channels in the range 63 to 33. Any bits above the actually implemented channels are reserved."]
56pub type Settrig63_33W<'a, REG> = crate::FieldWriter<'a, REG, 31, Settrig63_33>;
57impl<'a, REG> Settrig63_33W<'a, REG>
58where
59    REG: crate::Writable + crate::RegisterSpec,
60    REG::Ux: From<u32>,
61{
62    #[doc = "No effect."]
63    #[inline(always)]
64    pub fn no_effect(self) -> &'a mut crate::W<REG> {
65        self.variant(Settrig63_33::NoEffect)
66    }
67    #[doc = "Sets the Trig bit for DMA channel for the relevant DMA channel."]
68    #[inline(always)]
69    pub fn effect(self) -> &'a mut crate::W<REG> {
70        self.variant(Settrig63_33::Effect)
71    }
72}
73#[cfg(feature = "debug")]
74impl core::fmt::Debug for crate::generic::Reg<Settrig1Spec> {
75    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
76        write!(f, "(not readable)")
77    }
78}
79impl W {
80    #[doc = "Bit 0 - Set Trigger control bit for DMA channel 32."]
81    #[inline(always)]
82    pub fn settrig32(&mut self) -> Settrig32W<Settrig1Spec> {
83        Settrig32W::new(self, 0)
84    }
85    #[doc = "Bits 1:31 - Additional Set Trigger control bits for remaining DMA channels in the range 63 to 33. Any bits above the actually implemented channels are reserved."]
86    #[inline(always)]
87    pub fn settrig63_33(&mut self) -> Settrig63_33W<Settrig1Spec> {
88        Settrig63_33W::new(self, 1)
89    }
90}
91#[doc = "Set Trigger control bits for all DMA channels.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`settrig1::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct Settrig1Spec;
93impl crate::RegisterSpec for Settrig1Spec {
94    type Ux = u32;
95}
96#[doc = "`write(|w| ..)` method takes [`settrig1::W`](W) writer structure"]
97impl crate::Writable for Settrig1Spec {
98    type Safety = crate::Unsafe;
99    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
100    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
101}
102#[doc = "`reset()` method sets SETTRIG1 to value 0"]
103impl crate::Resettable for Settrig1Spec {
104    const RESET_VALUE: u32 = 0;
105}
mimxrt685s_pac/dma0/settrig1.rs

mimxrt685s_pac/dma0/
settrig1.rs
