mimxrt685s_pac/dma0/
intenset1.rs

1#[doc = "Register `INTENSET1` reader"]
2pub type R = crate::R<Intenset1Spec>;
3#[doc = "Register `INTENSET1` writer"]
4pub type W = crate::W<Intenset1Spec>;
5#[doc = "Interrupt Enable read and set for DMA channel 32.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Inten32 {
9    #[doc = "0: The Interrupt for DMA channel 32 is disabled."]
10    Disabled = 0,
11    #[doc = "1: The Interrupt for DMA channel 32 is enabled."]
12    Enabled = 1,
13}
14impl From<Inten32> for bool {
15    #[inline(always)]
16    fn from(variant: Inten32) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `INTEN32` reader - Interrupt Enable read and set for DMA channel 32."]
21pub type Inten32R = crate::BitReader<Inten32>;
22impl Inten32R {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Inten32 {
26        match self.bits {
27            false => Inten32::Disabled,
28            true => Inten32::Enabled,
29        }
30    }
31    #[doc = "The Interrupt for DMA channel 32 is disabled."]
32    #[inline(always)]
33    pub fn is_disabled(&self) -> bool {
34        *self == Inten32::Disabled
35    }
36    #[doc = "The Interrupt for DMA channel 32 is enabled."]
37    #[inline(always)]
38    pub fn is_enabled(&self) -> bool {
39        *self == Inten32::Enabled
40    }
41}
42#[doc = "Field `INTEN32` writer - Interrupt Enable read and set for DMA channel 32."]
43pub type Inten32W<'a, REG> = crate::BitWriter<'a, REG, Inten32>;
44impl<'a, REG> Inten32W<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "The Interrupt for DMA channel 32 is disabled."]
49    #[inline(always)]
50    pub fn disabled(self) -> &'a mut crate::W<REG> {
51        self.variant(Inten32::Disabled)
52    }
53    #[doc = "The Interrupt for DMA channel 32 is enabled."]
54    #[inline(always)]
55    pub fn enabled(self) -> &'a mut crate::W<REG> {
56        self.variant(Inten32::Enabled)
57    }
58}
59#[doc = "Additional Interrupt Enable read and set bits for remaining DMA channels in the range 63 to 33. Any bits above the actually implemented channels are reserved.\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62#[repr(u32)]
63pub enum Inten63_33 {
64    #[doc = "0: The Interrupt for the relevant DMA channel is disabled."]
65    Disabled = 0,
66    #[doc = "1: The Interrupt for the relevant DMA channel is enabled."]
67    Enabled = 1,
68}
69impl From<Inten63_33> for u32 {
70    #[inline(always)]
71    fn from(variant: Inten63_33) -> Self {
72        variant as _
73    }
74}
75impl crate::FieldSpec for Inten63_33 {
76    type Ux = u32;
77}
78impl crate::IsEnum for Inten63_33 {}
79#[doc = "Field `INTEN63_33` reader - Additional Interrupt Enable read and set bits for remaining DMA channels in the range 63 to 33. Any bits above the actually implemented channels are reserved."]
80pub type Inten63_33R = crate::FieldReader<Inten63_33>;
81impl Inten63_33R {
82    #[doc = "Get enumerated values variant"]
83    #[inline(always)]
84    pub const fn variant(&self) -> Option<Inten63_33> {
85        match self.bits {
86            0 => Some(Inten63_33::Disabled),
87            1 => Some(Inten63_33::Enabled),
88            _ => None,
89        }
90    }
91    #[doc = "The Interrupt for the relevant DMA channel is disabled."]
92    #[inline(always)]
93    pub fn is_disabled(&self) -> bool {
94        *self == Inten63_33::Disabled
95    }
96    #[doc = "The Interrupt for the relevant DMA channel is enabled."]
97    #[inline(always)]
98    pub fn is_enabled(&self) -> bool {
99        *self == Inten63_33::Enabled
100    }
101}
102#[doc = "Field `INTEN63_33` writer - Additional Interrupt Enable read and set bits for remaining DMA channels in the range 63 to 33. Any bits above the actually implemented channels are reserved."]
103pub type Inten63_33W<'a, REG> = crate::FieldWriter<'a, REG, 31, Inten63_33>;
104impl<'a, REG> Inten63_33W<'a, REG>
105where
106    REG: crate::Writable + crate::RegisterSpec,
107    REG::Ux: From<u32>,
108{
109    #[doc = "The Interrupt for the relevant DMA channel is disabled."]
110    #[inline(always)]
111    pub fn disabled(self) -> &'a mut crate::W<REG> {
112        self.variant(Inten63_33::Disabled)
113    }
114    #[doc = "The Interrupt for the relevant DMA channel is enabled."]
115    #[inline(always)]
116    pub fn enabled(self) -> &'a mut crate::W<REG> {
117        self.variant(Inten63_33::Enabled)
118    }
119}
120impl R {
121    #[doc = "Bit 0 - Interrupt Enable read and set for DMA channel 32."]
122    #[inline(always)]
123    pub fn inten32(&self) -> Inten32R {
124        Inten32R::new((self.bits & 1) != 0)
125    }
126    #[doc = "Bits 1:31 - Additional Interrupt Enable read and set bits for remaining DMA channels in the range 63 to 33. Any bits above the actually implemented channels are reserved."]
127    #[inline(always)]
128    pub fn inten63_33(&self) -> Inten63_33R {
129        Inten63_33R::new((self.bits >> 1) & 0x7fff_ffff)
130    }
131}
132#[cfg(feature = "debug")]
133impl core::fmt::Debug for R {
134    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
135        f.debug_struct("INTENSET1")
136            .field("inten32", &self.inten32())
137            .field("inten63_33", &self.inten63_33())
138            .finish()
139    }
140}
141impl W {
142    #[doc = "Bit 0 - Interrupt Enable read and set for DMA channel 32."]
143    #[inline(always)]
144    pub fn inten32(&mut self) -> Inten32W<Intenset1Spec> {
145        Inten32W::new(self, 0)
146    }
147    #[doc = "Bits 1:31 - Additional Interrupt Enable read and set bits for remaining DMA channels in the range 63 to 33. Any bits above the actually implemented channels are reserved."]
148    #[inline(always)]
149    pub fn inten63_33(&mut self) -> Inten63_33W<Intenset1Spec> {
150        Inten63_33W::new(self, 1)
151    }
152}
153#[doc = "Interrupt Enable read and Set for all DMA channels.\n\nYou can [`read`](crate::Reg::read) this register and get [`intenset1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenset1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
154pub struct Intenset1Spec;
155impl crate::RegisterSpec for Intenset1Spec {
156    type Ux = u32;
157}
158#[doc = "`read()` method returns [`intenset1::R`](R) reader structure"]
159impl crate::Readable for Intenset1Spec {}
160#[doc = "`write(|w| ..)` method takes [`intenset1::W`](W) writer structure"]
161impl crate::Writable for Intenset1Spec {
162    type Safety = crate::Unsafe;
163    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
164    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
165}
166#[doc = "`reset()` method sets INTENSET1 to value 0"]
167impl crate::Resettable for Intenset1Spec {
168    const RESET_VALUE: u32 = 0;
169}
mimxrt685s_pac/dma0/intenset1.rs

mimxrt685s_pac/dma0/
intenset1.rs
