mimxrt685s_pac/dma0/
inta0.rs

1#[doc = "Register `INTA0` reader"]
2pub type R = crate::R<Inta0Spec>;
3#[doc = "Register `INTA0` writer"]
4pub type W = crate::W<Inta0Spec>;
5#[doc = "Interrupt A status for DMA channel 0.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u32)]
9pub enum Ia {
10    #[doc = "0: The DMAchannel 0 interrupt A is not active."]
11    NotActive = 0,
12    #[doc = "1: The DMAchannel 0 interrupt A is active."]
13    Active = 1,
14}
15impl From<Ia> for u32 {
16    #[inline(always)]
17    fn from(variant: Ia) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for Ia {
22    type Ux = u32;
23}
24impl crate::IsEnum for Ia {}
25#[doc = "Field `IA` reader - Interrupt A status for DMA channel 0."]
26pub type IaR = crate::FieldReader<Ia>;
27impl IaR {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<Ia> {
31        match self.bits {
32            0 => Some(Ia::NotActive),
33            1 => Some(Ia::Active),
34            _ => None,
35        }
36    }
37    #[doc = "The DMAchannel 0 interrupt A is not active."]
38    #[inline(always)]
39    pub fn is_not_active(&self) -> bool {
40        *self == Ia::NotActive
41    }
42    #[doc = "The DMAchannel 0 interrupt A is active."]
43    #[inline(always)]
44    pub fn is_active(&self) -> bool {
45        *self == Ia::Active
46    }
47}
48#[doc = "Field `IA` writer - Interrupt A status for DMA channel 0."]
49pub type IaW<'a, REG> = crate::FieldWriter<'a, REG, 32, Ia>;
50impl<'a, REG> IaW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53    REG::Ux: From<u32>,
54{
55    #[doc = "The DMAchannel 0 interrupt A is not active."]
56    #[inline(always)]
57    pub fn not_active(self) -> &'a mut crate::W<REG> {
58        self.variant(Ia::NotActive)
59    }
60    #[doc = "The DMAchannel 0 interrupt A is active."]
61    #[inline(always)]
62    pub fn active(self) -> &'a mut crate::W<REG> {
63        self.variant(Ia::Active)
64    }
65}
66impl R {
67    #[doc = "Bits 0:31 - Interrupt A status for DMA channel 0."]
68    #[inline(always)]
69    pub fn ia(&self) -> IaR {
70        IaR::new(self.bits)
71    }
72}
73#[cfg(feature = "debug")]
74impl core::fmt::Debug for R {
75    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
76        f.debug_struct("INTA0").field("ia", &self.ia()).finish()
77    }
78}
79impl W {
80    #[doc = "Bits 0:31 - Interrupt A status for DMA channel 0."]
81    #[inline(always)]
82    pub fn ia(&mut self) -> IaW<Inta0Spec> {
83        IaW::new(self, 0)
84    }
85}
86#[doc = "Interrupt A status for all DMA channels.\n\nYou can [`read`](crate::Reg::read) this register and get [`inta0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inta0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
87pub struct Inta0Spec;
88impl crate::RegisterSpec for Inta0Spec {
89    type Ux = u32;
90}
91#[doc = "`read()` method returns [`inta0::R`](R) reader structure"]
92impl crate::Readable for Inta0Spec {}
93#[doc = "`write(|w| ..)` method takes [`inta0::W`](W) writer structure"]
94impl crate::Writable for Inta0Spec {
95    type Safety = crate::Unsafe;
96    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
97    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
98}
99#[doc = "`reset()` method sets INTA0 to value 0"]
100impl crate::Resettable for Inta0Spec {
101    const RESET_VALUE: u32 = 0;
102}
mimxrt685s_pac/dma0/inta0.rs

mimxrt685s_pac/dma0/
inta0.rs
