mimxrt685s_pac/dma0/
errint0.rs

1#[doc = "Register `ERRINT0` reader"]
2pub type R = crate::R<Errint0Spec>;
3#[doc = "Register `ERRINT0` writer"]
4pub type W = crate::W<Errint0Spec>;
5#[doc = "Error Interrupt flag for DMA channel 0.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u32)]
9pub enum Err {
10    #[doc = "0: The Error Interrupt is not active for DMA channel 0."]
11    NotActive = 0,
12    #[doc = "1: The Error Interrupt is pending for DMA channel 0."]
13    Pending = 1,
14}
15impl From<Err> for u32 {
16    #[inline(always)]
17    fn from(variant: Err) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for Err {
22    type Ux = u32;
23}
24impl crate::IsEnum for Err {}
25#[doc = "Field `ERR` reader - Error Interrupt flag for DMA channel 0."]
26pub type ErrR = crate::FieldReader<Err>;
27impl ErrR {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<Err> {
31        match self.bits {
32            0 => Some(Err::NotActive),
33            1 => Some(Err::Pending),
34            _ => None,
35        }
36    }
37    #[doc = "The Error Interrupt is not active for DMA channel 0."]
38    #[inline(always)]
39    pub fn is_not_active(&self) -> bool {
40        *self == Err::NotActive
41    }
42    #[doc = "The Error Interrupt is pending for DMA channel 0."]
43    #[inline(always)]
44    pub fn is_pending(&self) -> bool {
45        *self == Err::Pending
46    }
47}
48#[doc = "Field `ERR` writer - Error Interrupt flag for DMA channel 0."]
49pub type ErrW<'a, REG> = crate::FieldWriter<'a, REG, 32, Err>;
50impl<'a, REG> ErrW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53    REG::Ux: From<u32>,
54{
55    #[doc = "The Error Interrupt is not active for DMA channel 0."]
56    #[inline(always)]
57    pub fn not_active(self) -> &'a mut crate::W<REG> {
58        self.variant(Err::NotActive)
59    }
60    #[doc = "The Error Interrupt is pending for DMA channel 0."]
61    #[inline(always)]
62    pub fn pending(self) -> &'a mut crate::W<REG> {
63        self.variant(Err::Pending)
64    }
65}
66impl R {
67    #[doc = "Bits 0:31 - Error Interrupt flag for DMA channel 0."]
68    #[inline(always)]
69    pub fn err(&self) -> ErrR {
70        ErrR::new(self.bits)
71    }
72}
73#[cfg(feature = "debug")]
74impl core::fmt::Debug for R {
75    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
76        f.debug_struct("ERRINT0").field("err", &self.err()).finish()
77    }
78}
79impl W {
80    #[doc = "Bits 0:31 - Error Interrupt flag for DMA channel 0."]
81    #[inline(always)]
82    pub fn err(&mut self) -> ErrW<Errint0Spec> {
83        ErrW::new(self, 0)
84    }
85}
86#[doc = "Error Interrupt status for all DMA channels.\n\nYou can [`read`](crate::Reg::read) this register and get [`errint0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`errint0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
87pub struct Errint0Spec;
88impl crate::RegisterSpec for Errint0Spec {
89    type Ux = u32;
90}
91#[doc = "`read()` method returns [`errint0::R`](R) reader structure"]
92impl crate::Readable for Errint0Spec {}
93#[doc = "`write(|w| ..)` method takes [`errint0::W`](W) writer structure"]
94impl crate::Writable for Errint0Spec {
95    type Safety = crate::Unsafe;
96    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
97    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
98}
99#[doc = "`reset()` method sets ERRINT0 to value 0"]
100impl crate::Resettable for Errint0Spec {
101    const RESET_VALUE: u32 = 0;
102}
mimxrt685s_pac/dma0/errint0.rs

mimxrt685s_pac/dma0/
errint0.rs
