mimxrt685s_pac/dma0/
enableset0.rs

1#[doc = "Register `ENABLESET0` reader"]
2pub type R = crate::R<Enableset0Spec>;
3#[doc = "Register `ENABLESET0` writer"]
4pub type W = crate::W<Enableset0Spec>;
5#[doc = "Enable for DMA channel 0\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u32)]
9pub enum Ena {
10    #[doc = "0: DMAchannel 0 is disabled."]
11    Disabled = 0,
12    #[doc = "1: DMAchannel 0 is enabled."]
13    Enabled = 1,
14}
15impl From<Ena> for u32 {
16    #[inline(always)]
17    fn from(variant: Ena) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for Ena {
22    type Ux = u32;
23}
24impl crate::IsEnum for Ena {}
25#[doc = "Field `ENA` reader - Enable for DMA channel 0"]
26pub type EnaR = crate::FieldReader<Ena>;
27impl EnaR {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<Ena> {
31        match self.bits {
32            0 => Some(Ena::Disabled),
33            1 => Some(Ena::Enabled),
34            _ => None,
35        }
36    }
37    #[doc = "DMAchannel 0 is disabled."]
38    #[inline(always)]
39    pub fn is_disabled(&self) -> bool {
40        *self == Ena::Disabled
41    }
42    #[doc = "DMAchannel 0 is enabled."]
43    #[inline(always)]
44    pub fn is_enabled(&self) -> bool {
45        *self == Ena::Enabled
46    }
47}
48#[doc = "Field `ENA` writer - Enable for DMA channel 0"]
49pub type EnaW<'a, REG> = crate::FieldWriter<'a, REG, 32, Ena>;
50impl<'a, REG> EnaW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53    REG::Ux: From<u32>,
54{
55    #[doc = "DMAchannel 0 is disabled."]
56    #[inline(always)]
57    pub fn disabled(self) -> &'a mut crate::W<REG> {
58        self.variant(Ena::Disabled)
59    }
60    #[doc = "DMAchannel 0 is enabled."]
61    #[inline(always)]
62    pub fn enabled(self) -> &'a mut crate::W<REG> {
63        self.variant(Ena::Enabled)
64    }
65}
66impl R {
67    #[doc = "Bits 0:31 - Enable for DMA channel 0"]
68    #[inline(always)]
69    pub fn ena(&self) -> EnaR {
70        EnaR::new(self.bits)
71    }
72}
73#[cfg(feature = "debug")]
74impl core::fmt::Debug for R {
75    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
76        f.debug_struct("ENABLESET0")
77            .field("ena", &self.ena())
78            .finish()
79    }
80}
81impl W {
82    #[doc = "Bits 0:31 - Enable for DMA channel 0"]
83    #[inline(always)]
84    pub fn ena(&mut self) -> EnaW<Enableset0Spec> {
85        EnaW::new(self, 0)
86    }
87}
88#[doc = "Channel Enable read and Set for all DMA channels.\n\nYou can [`read`](crate::Reg::read) this register and get [`enableset0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`enableset0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
89pub struct Enableset0Spec;
90impl crate::RegisterSpec for Enableset0Spec {
91    type Ux = u32;
92}
93#[doc = "`read()` method returns [`enableset0::R`](R) reader structure"]
94impl crate::Readable for Enableset0Spec {}
95#[doc = "`write(|w| ..)` method takes [`enableset0::W`](W) writer structure"]
96impl crate::Writable for Enableset0Spec {
97    type Safety = crate::Unsafe;
98    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
99    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
100}
101#[doc = "`reset()` method sets ENABLESET0 to value 0"]
102impl crate::Resettable for Enableset0Spec {
103    const RESET_VALUE: u32 = 0;
104}
mimxrt685s_pac/dma0/enableset0.rs

mimxrt685s_pac/dma0/
enableset0.rs
