1#[doc = "Register `XFERCFG` reader"]
2pub type R = crate::R<XfercfgSpec>;
3#[doc = "Register `XFERCFG` writer"]
4pub type W = crate::W<XfercfgSpec>;
5#[doc = "Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Cfgvalid {
9 #[doc = "0: Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting."]
10 NotValid = 0,
11 #[doc = "1: Valid. The current channel descriptor is considered valid."]
12 Valid = 1,
13}
14impl From<Cfgvalid> for bool {
15 #[inline(always)]
16 fn from(variant: Cfgvalid) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `CFGVALID` reader - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."]
21pub type CfgvalidR = crate::BitReader<Cfgvalid>;
22impl CfgvalidR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> Cfgvalid {
26 match self.bits {
27 false => Cfgvalid::NotValid,
28 true => Cfgvalid::Valid,
29 }
30 }
31 #[doc = "Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting."]
32 #[inline(always)]
33 pub fn is_not_valid(&self) -> bool {
34 *self == Cfgvalid::NotValid
35 }
36 #[doc = "Valid. The current channel descriptor is considered valid."]
37 #[inline(always)]
38 pub fn is_valid(&self) -> bool {
39 *self == Cfgvalid::Valid
40 }
41}
42#[doc = "Field `CFGVALID` writer - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."]
43pub type CfgvalidW<'a, REG> = crate::BitWriter<'a, REG, Cfgvalid>;
44impl<'a, REG> CfgvalidW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting."]
49 #[inline(always)]
50 pub fn not_valid(self) -> &'a mut crate::W<REG> {
51 self.variant(Cfgvalid::NotValid)
52 }
53 #[doc = "Valid. The current channel descriptor is considered valid."]
54 #[inline(always)]
55 pub fn valid(self) -> &'a mut crate::W<REG> {
56 self.variant(Cfgvalid::Valid)
57 }
58}
59#[doc = "Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Reload {
63 #[doc = "0: Disabled. Do not reload the channels' control structure when the current descriptor is exhausted."]
64 Disabled = 0,
65 #[doc = "1: Enabled. Reload the channels' control structure when the current descriptor is exhausted."]
66 Enabled = 1,
67}
68impl From<Reload> for bool {
69 #[inline(always)]
70 fn from(variant: Reload) -> Self {
71 variant as u8 != 0
72 }
73}
74#[doc = "Field `RELOAD` reader - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."]
75pub type ReloadR = crate::BitReader<Reload>;
76impl ReloadR {
77 #[doc = "Get enumerated values variant"]
78 #[inline(always)]
79 pub const fn variant(&self) -> Reload {
80 match self.bits {
81 false => Reload::Disabled,
82 true => Reload::Enabled,
83 }
84 }
85 #[doc = "Disabled. Do not reload the channels' control structure when the current descriptor is exhausted."]
86 #[inline(always)]
87 pub fn is_disabled(&self) -> bool {
88 *self == Reload::Disabled
89 }
90 #[doc = "Enabled. Reload the channels' control structure when the current descriptor is exhausted."]
91 #[inline(always)]
92 pub fn is_enabled(&self) -> bool {
93 *self == Reload::Enabled
94 }
95}
96#[doc = "Field `RELOAD` writer - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."]
97pub type ReloadW<'a, REG> = crate::BitWriter<'a, REG, Reload>;
98impl<'a, REG> ReloadW<'a, REG>
99where
100 REG: crate::Writable + crate::RegisterSpec,
101{
102 #[doc = "Disabled. Do not reload the channels' control structure when the current descriptor is exhausted."]
103 #[inline(always)]
104 pub fn disabled(self) -> &'a mut crate::W<REG> {
105 self.variant(Reload::Disabled)
106 }
107 #[doc = "Enabled. Reload the channels' control structure when the current descriptor is exhausted."]
108 #[inline(always)]
109 pub fn enabled(self) -> &'a mut crate::W<REG> {
110 self.variant(Reload::Enabled)
111 }
112}
113#[doc = "Software Trigger.\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Swtrig {
117 #[doc = "0: Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel."]
118 NotSet = 0,
119 #[doc = "1: Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0."]
120 Set = 1,
121}
122impl From<Swtrig> for bool {
123 #[inline(always)]
124 fn from(variant: Swtrig) -> Self {
125 variant as u8 != 0
126 }
127}
128#[doc = "Field `SWTRIG` reader - Software Trigger."]
129pub type SwtrigR = crate::BitReader<Swtrig>;
130impl SwtrigR {
131 #[doc = "Get enumerated values variant"]
132 #[inline(always)]
133 pub const fn variant(&self) -> Swtrig {
134 match self.bits {
135 false => Swtrig::NotSet,
136 true => Swtrig::Set,
137 }
138 }
139 #[doc = "Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel."]
140 #[inline(always)]
141 pub fn is_not_set(&self) -> bool {
142 *self == Swtrig::NotSet
143 }
144 #[doc = "Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0."]
145 #[inline(always)]
146 pub fn is_set(&self) -> bool {
147 *self == Swtrig::Set
148 }
149}
150#[doc = "Field `SWTRIG` writer - Software Trigger."]
151pub type SwtrigW<'a, REG> = crate::BitWriter<'a, REG, Swtrig>;
152impl<'a, REG> SwtrigW<'a, REG>
153where
154 REG: crate::Writable + crate::RegisterSpec,
155{
156 #[doc = "Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel."]
157 #[inline(always)]
158 pub fn not_set(self) -> &'a mut crate::W<REG> {
159 self.variant(Swtrig::NotSet)
160 }
161 #[doc = "Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0."]
162 #[inline(always)]
163 pub fn set_(self) -> &'a mut crate::W<REG> {
164 self.variant(Swtrig::Set)
165 }
166}
167#[doc = "Clear Trigger.\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Clrtrig {
171 #[doc = "0: Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started."]
172 NotCleared = 0,
173 #[doc = "1: Cleared. The trigger is cleared when this descriptor is exhausted"]
174 Cleared = 1,
175}
176impl From<Clrtrig> for bool {
177 #[inline(always)]
178 fn from(variant: Clrtrig) -> Self {
179 variant as u8 != 0
180 }
181}
182#[doc = "Field `CLRTRIG` reader - Clear Trigger."]
183pub type ClrtrigR = crate::BitReader<Clrtrig>;
184impl ClrtrigR {
185 #[doc = "Get enumerated values variant"]
186 #[inline(always)]
187 pub const fn variant(&self) -> Clrtrig {
188 match self.bits {
189 false => Clrtrig::NotCleared,
190 true => Clrtrig::Cleared,
191 }
192 }
193 #[doc = "Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started."]
194 #[inline(always)]
195 pub fn is_not_cleared(&self) -> bool {
196 *self == Clrtrig::NotCleared
197 }
198 #[doc = "Cleared. The trigger is cleared when this descriptor is exhausted"]
199 #[inline(always)]
200 pub fn is_cleared(&self) -> bool {
201 *self == Clrtrig::Cleared
202 }
203}
204#[doc = "Field `CLRTRIG` writer - Clear Trigger."]
205pub type ClrtrigW<'a, REG> = crate::BitWriter<'a, REG, Clrtrig>;
206impl<'a, REG> ClrtrigW<'a, REG>
207where
208 REG: crate::Writable + crate::RegisterSpec,
209{
210 #[doc = "Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started."]
211 #[inline(always)]
212 pub fn not_cleared(self) -> &'a mut crate::W<REG> {
213 self.variant(Clrtrig::NotCleared)
214 }
215 #[doc = "Cleared. The trigger is cleared when this descriptor is exhausted"]
216 #[inline(always)]
217 pub fn cleared(self) -> &'a mut crate::W<REG> {
218 self.variant(Clrtrig::Cleared)
219 }
220}
221#[doc = "Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum Setinta {
225 #[doc = "0: No effect."]
226 NoEffect = 0,
227 #[doc = "1: Set. The INTA flag for this channel will be set when the current descriptor is exhausted."]
228 Set = 1,
229}
230impl From<Setinta> for bool {
231 #[inline(always)]
232 fn from(variant: Setinta) -> Self {
233 variant as u8 != 0
234 }
235}
236#[doc = "Field `SETINTA` reader - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
237pub type SetintaR = crate::BitReader<Setinta>;
238impl SetintaR {
239 #[doc = "Get enumerated values variant"]
240 #[inline(always)]
241 pub const fn variant(&self) -> Setinta {
242 match self.bits {
243 false => Setinta::NoEffect,
244 true => Setinta::Set,
245 }
246 }
247 #[doc = "No effect."]
248 #[inline(always)]
249 pub fn is_no_effect(&self) -> bool {
250 *self == Setinta::NoEffect
251 }
252 #[doc = "Set. The INTA flag for this channel will be set when the current descriptor is exhausted."]
253 #[inline(always)]
254 pub fn is_set(&self) -> bool {
255 *self == Setinta::Set
256 }
257}
258#[doc = "Field `SETINTA` writer - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
259pub type SetintaW<'a, REG> = crate::BitWriter<'a, REG, Setinta>;
260impl<'a, REG> SetintaW<'a, REG>
261where
262 REG: crate::Writable + crate::RegisterSpec,
263{
264 #[doc = "No effect."]
265 #[inline(always)]
266 pub fn no_effect(self) -> &'a mut crate::W<REG> {
267 self.variant(Setinta::NoEffect)
268 }
269 #[doc = "Set. The INTA flag for this channel will be set when the current descriptor is exhausted."]
270 #[inline(always)]
271 pub fn set_(self) -> &'a mut crate::W<REG> {
272 self.variant(Setinta::Set)
273 }
274}
275#[doc = "Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.\n\nValue on reset: 0"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum Setintb {
279 #[doc = "0: No effect."]
280 NoEffect = 0,
281 #[doc = "1: Set. The INTB flag for this channel will be set when the current descriptor is exhausted."]
282 Set = 1,
283}
284impl From<Setintb> for bool {
285 #[inline(always)]
286 fn from(variant: Setintb) -> Self {
287 variant as u8 != 0
288 }
289}
290#[doc = "Field `SETINTB` reader - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
291pub type SetintbR = crate::BitReader<Setintb>;
292impl SetintbR {
293 #[doc = "Get enumerated values variant"]
294 #[inline(always)]
295 pub const fn variant(&self) -> Setintb {
296 match self.bits {
297 false => Setintb::NoEffect,
298 true => Setintb::Set,
299 }
300 }
301 #[doc = "No effect."]
302 #[inline(always)]
303 pub fn is_no_effect(&self) -> bool {
304 *self == Setintb::NoEffect
305 }
306 #[doc = "Set. The INTB flag for this channel will be set when the current descriptor is exhausted."]
307 #[inline(always)]
308 pub fn is_set(&self) -> bool {
309 *self == Setintb::Set
310 }
311}
312#[doc = "Field `SETINTB` writer - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
313pub type SetintbW<'a, REG> = crate::BitWriter<'a, REG, Setintb>;
314impl<'a, REG> SetintbW<'a, REG>
315where
316 REG: crate::Writable + crate::RegisterSpec,
317{
318 #[doc = "No effect."]
319 #[inline(always)]
320 pub fn no_effect(self) -> &'a mut crate::W<REG> {
321 self.variant(Setintb::NoEffect)
322 }
323 #[doc = "Set. The INTB flag for this channel will be set when the current descriptor is exhausted."]
324 #[inline(always)]
325 pub fn set_(self) -> &'a mut crate::W<REG> {
326 self.variant(Setintb::Set)
327 }
328}
329#[doc = "Transfer width used for this DMA channel.\n\nValue on reset: 0"]
330#[cfg_attr(feature = "defmt", derive(defmt::Format))]
331#[derive(Clone, Copy, Debug, PartialEq, Eq)]
332#[repr(u8)]
333pub enum Width {
334 #[doc = "0: 8-bit. 8-bit transfers are performed (8-bit source reads and destination writes)."]
335 Bit8 = 0,
336 #[doc = "1: 16-bit. 6-bit transfers are performed (16-bit source reads and destination writes)."]
337 Bit16 = 1,
338 #[doc = "2: 32-bit. 32-bit transfers are performed (32-bit source reads and destination writes)."]
339 Bit32 = 2,
340}
341impl From<Width> for u8 {
342 #[inline(always)]
343 fn from(variant: Width) -> Self {
344 variant as _
345 }
346}
347impl crate::FieldSpec for Width {
348 type Ux = u8;
349}
350impl crate::IsEnum for Width {}
351#[doc = "Field `WIDTH` reader - Transfer width used for this DMA channel."]
352pub type WidthR = crate::FieldReader<Width>;
353impl WidthR {
354 #[doc = "Get enumerated values variant"]
355 #[inline(always)]
356 pub const fn variant(&self) -> Option<Width> {
357 match self.bits {
358 0 => Some(Width::Bit8),
359 1 => Some(Width::Bit16),
360 2 => Some(Width::Bit32),
361 _ => None,
362 }
363 }
364 #[doc = "8-bit. 8-bit transfers are performed (8-bit source reads and destination writes)."]
365 #[inline(always)]
366 pub fn is_bit_8(&self) -> bool {
367 *self == Width::Bit8
368 }
369 #[doc = "16-bit. 6-bit transfers are performed (16-bit source reads and destination writes)."]
370 #[inline(always)]
371 pub fn is_bit_16(&self) -> bool {
372 *self == Width::Bit16
373 }
374 #[doc = "32-bit. 32-bit transfers are performed (32-bit source reads and destination writes)."]
375 #[inline(always)]
376 pub fn is_bit_32(&self) -> bool {
377 *self == Width::Bit32
378 }
379}
380#[doc = "Field `WIDTH` writer - Transfer width used for this DMA channel."]
381pub type WidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, Width>;
382impl<'a, REG> WidthW<'a, REG>
383where
384 REG: crate::Writable + crate::RegisterSpec,
385 REG::Ux: From<u8>,
386{
387 #[doc = "8-bit. 8-bit transfers are performed (8-bit source reads and destination writes)."]
388 #[inline(always)]
389 pub fn bit_8(self) -> &'a mut crate::W<REG> {
390 self.variant(Width::Bit8)
391 }
392 #[doc = "16-bit. 6-bit transfers are performed (16-bit source reads and destination writes)."]
393 #[inline(always)]
394 pub fn bit_16(self) -> &'a mut crate::W<REG> {
395 self.variant(Width::Bit16)
396 }
397 #[doc = "32-bit. 32-bit transfers are performed (32-bit source reads and destination writes)."]
398 #[inline(always)]
399 pub fn bit_32(self) -> &'a mut crate::W<REG> {
400 self.variant(Width::Bit32)
401 }
402}
403#[doc = "Determines whether the source address is incremented for each DMA transfer.\n\nValue on reset: 0"]
404#[cfg_attr(feature = "defmt", derive(defmt::Format))]
405#[derive(Clone, Copy, Debug, PartialEq, Eq)]
406#[repr(u8)]
407pub enum Srcinc {
408 #[doc = "0: No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device."]
409 NoIncrement = 0,
410 #[doc = "1: 1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory."]
411 WidthX1 = 1,
412 #[doc = "2: 2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer."]
413 WidthX2 = 2,
414 #[doc = "3: 4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer."]
415 WidthX4 = 3,
416}
417impl From<Srcinc> for u8 {
418 #[inline(always)]
419 fn from(variant: Srcinc) -> Self {
420 variant as _
421 }
422}
423impl crate::FieldSpec for Srcinc {
424 type Ux = u8;
425}
426impl crate::IsEnum for Srcinc {}
427#[doc = "Field `SRCINC` reader - Determines whether the source address is incremented for each DMA transfer."]
428pub type SrcincR = crate::FieldReader<Srcinc>;
429impl SrcincR {
430 #[doc = "Get enumerated values variant"]
431 #[inline(always)]
432 pub const fn variant(&self) -> Srcinc {
433 match self.bits {
434 0 => Srcinc::NoIncrement,
435 1 => Srcinc::WidthX1,
436 2 => Srcinc::WidthX2,
437 3 => Srcinc::WidthX4,
438 _ => unreachable!(),
439 }
440 }
441 #[doc = "No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device."]
442 #[inline(always)]
443 pub fn is_no_increment(&self) -> bool {
444 *self == Srcinc::NoIncrement
445 }
446 #[doc = "1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory."]
447 #[inline(always)]
448 pub fn is_width_x_1(&self) -> bool {
449 *self == Srcinc::WidthX1
450 }
451 #[doc = "2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer."]
452 #[inline(always)]
453 pub fn is_width_x_2(&self) -> bool {
454 *self == Srcinc::WidthX2
455 }
456 #[doc = "4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer."]
457 #[inline(always)]
458 pub fn is_width_x_4(&self) -> bool {
459 *self == Srcinc::WidthX4
460 }
461}
462#[doc = "Field `SRCINC` writer - Determines whether the source address is incremented for each DMA transfer."]
463pub type SrcincW<'a, REG> = crate::FieldWriter<'a, REG, 2, Srcinc, crate::Safe>;
464impl<'a, REG> SrcincW<'a, REG>
465where
466 REG: crate::Writable + crate::RegisterSpec,
467 REG::Ux: From<u8>,
468{
469 #[doc = "No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device."]
470 #[inline(always)]
471 pub fn no_increment(self) -> &'a mut crate::W<REG> {
472 self.variant(Srcinc::NoIncrement)
473 }
474 #[doc = "1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory."]
475 #[inline(always)]
476 pub fn width_x_1(self) -> &'a mut crate::W<REG> {
477 self.variant(Srcinc::WidthX1)
478 }
479 #[doc = "2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer."]
480 #[inline(always)]
481 pub fn width_x_2(self) -> &'a mut crate::W<REG> {
482 self.variant(Srcinc::WidthX2)
483 }
484 #[doc = "4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer."]
485 #[inline(always)]
486 pub fn width_x_4(self) -> &'a mut crate::W<REG> {
487 self.variant(Srcinc::WidthX4)
488 }
489}
490#[doc = "Determines whether the destination address is incremented for each DMA transfer.\n\nValue on reset: 0"]
491#[cfg_attr(feature = "defmt", derive(defmt::Format))]
492#[derive(Clone, Copy, Debug, PartialEq, Eq)]
493#[repr(u8)]
494pub enum Dstinc {
495 #[doc = "0: No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device."]
496 NoIncrement = 0,
497 #[doc = "1: 1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory."]
498 WidthX1 = 1,
499 #[doc = "2: 2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer."]
500 WidthX2 = 2,
501 #[doc = "3: 4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer."]
502 WidthX4 = 3,
503}
504impl From<Dstinc> for u8 {
505 #[inline(always)]
506 fn from(variant: Dstinc) -> Self {
507 variant as _
508 }
509}
510impl crate::FieldSpec for Dstinc {
511 type Ux = u8;
512}
513impl crate::IsEnum for Dstinc {}
514#[doc = "Field `DSTINC` reader - Determines whether the destination address is incremented for each DMA transfer."]
515pub type DstincR = crate::FieldReader<Dstinc>;
516impl DstincR {
517 #[doc = "Get enumerated values variant"]
518 #[inline(always)]
519 pub const fn variant(&self) -> Dstinc {
520 match self.bits {
521 0 => Dstinc::NoIncrement,
522 1 => Dstinc::WidthX1,
523 2 => Dstinc::WidthX2,
524 3 => Dstinc::WidthX4,
525 _ => unreachable!(),
526 }
527 }
528 #[doc = "No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device."]
529 #[inline(always)]
530 pub fn is_no_increment(&self) -> bool {
531 *self == Dstinc::NoIncrement
532 }
533 #[doc = "1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory."]
534 #[inline(always)]
535 pub fn is_width_x_1(&self) -> bool {
536 *self == Dstinc::WidthX1
537 }
538 #[doc = "2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer."]
539 #[inline(always)]
540 pub fn is_width_x_2(&self) -> bool {
541 *self == Dstinc::WidthX2
542 }
543 #[doc = "4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer."]
544 #[inline(always)]
545 pub fn is_width_x_4(&self) -> bool {
546 *self == Dstinc::WidthX4
547 }
548}
549#[doc = "Field `DSTINC` writer - Determines whether the destination address is incremented for each DMA transfer."]
550pub type DstincW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dstinc, crate::Safe>;
551impl<'a, REG> DstincW<'a, REG>
552where
553 REG: crate::Writable + crate::RegisterSpec,
554 REG::Ux: From<u8>,
555{
556 #[doc = "No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device."]
557 #[inline(always)]
558 pub fn no_increment(self) -> &'a mut crate::W<REG> {
559 self.variant(Dstinc::NoIncrement)
560 }
561 #[doc = "1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory."]
562 #[inline(always)]
563 pub fn width_x_1(self) -> &'a mut crate::W<REG> {
564 self.variant(Dstinc::WidthX1)
565 }
566 #[doc = "2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer."]
567 #[inline(always)]
568 pub fn width_x_2(self) -> &'a mut crate::W<REG> {
569 self.variant(Dstinc::WidthX2)
570 }
571 #[doc = "4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer."]
572 #[inline(always)]
573 pub fn width_x_4(self) -> &'a mut crate::W<REG> {
574 self.variant(Dstinc::WidthX4)
575 }
576}
577#[doc = "Field `XFERCOUNT` reader - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed."]
578pub type XfercountR = crate::FieldReader<u16>;
579#[doc = "Field `XFERCOUNT` writer - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed."]
580pub type XfercountW<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
581impl R {
582 #[doc = "Bit 0 - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."]
583 #[inline(always)]
584 pub fn cfgvalid(&self) -> CfgvalidR {
585 CfgvalidR::new((self.bits & 1) != 0)
586 }
587 #[doc = "Bit 1 - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."]
588 #[inline(always)]
589 pub fn reload(&self) -> ReloadR {
590 ReloadR::new(((self.bits >> 1) & 1) != 0)
591 }
592 #[doc = "Bit 2 - Software Trigger."]
593 #[inline(always)]
594 pub fn swtrig(&self) -> SwtrigR {
595 SwtrigR::new(((self.bits >> 2) & 1) != 0)
596 }
597 #[doc = "Bit 3 - Clear Trigger."]
598 #[inline(always)]
599 pub fn clrtrig(&self) -> ClrtrigR {
600 ClrtrigR::new(((self.bits >> 3) & 1) != 0)
601 }
602 #[doc = "Bit 4 - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
603 #[inline(always)]
604 pub fn setinta(&self) -> SetintaR {
605 SetintaR::new(((self.bits >> 4) & 1) != 0)
606 }
607 #[doc = "Bit 5 - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
608 #[inline(always)]
609 pub fn setintb(&self) -> SetintbR {
610 SetintbR::new(((self.bits >> 5) & 1) != 0)
611 }
612 #[doc = "Bits 8:9 - Transfer width used for this DMA channel."]
613 #[inline(always)]
614 pub fn width(&self) -> WidthR {
615 WidthR::new(((self.bits >> 8) & 3) as u8)
616 }
617 #[doc = "Bits 12:13 - Determines whether the source address is incremented for each DMA transfer."]
618 #[inline(always)]
619 pub fn srcinc(&self) -> SrcincR {
620 SrcincR::new(((self.bits >> 12) & 3) as u8)
621 }
622 #[doc = "Bits 14:15 - Determines whether the destination address is incremented for each DMA transfer."]
623 #[inline(always)]
624 pub fn dstinc(&self) -> DstincR {
625 DstincR::new(((self.bits >> 14) & 3) as u8)
626 }
627 #[doc = "Bits 16:25 - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed."]
628 #[inline(always)]
629 pub fn xfercount(&self) -> XfercountR {
630 XfercountR::new(((self.bits >> 16) & 0x03ff) as u16)
631 }
632}
633#[cfg(feature = "debug")]
634impl core::fmt::Debug for R {
635 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
636 f.debug_struct("XFERCFG")
637 .field("cfgvalid", &self.cfgvalid())
638 .field("reload", &self.reload())
639 .field("swtrig", &self.swtrig())
640 .field("clrtrig", &self.clrtrig())
641 .field("setinta", &self.setinta())
642 .field("setintb", &self.setintb())
643 .field("width", &self.width())
644 .field("srcinc", &self.srcinc())
645 .field("dstinc", &self.dstinc())
646 .field("xfercount", &self.xfercount())
647 .finish()
648 }
649}
650impl W {
651 #[doc = "Bit 0 - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled."]
652 #[inline(always)]
653 pub fn cfgvalid(&mut self) -> CfgvalidW<XfercfgSpec> {
654 CfgvalidW::new(self, 0)
655 }
656 #[doc = "Bit 1 - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers."]
657 #[inline(always)]
658 pub fn reload(&mut self) -> ReloadW<XfercfgSpec> {
659 ReloadW::new(self, 1)
660 }
661 #[doc = "Bit 2 - Software Trigger."]
662 #[inline(always)]
663 pub fn swtrig(&mut self) -> SwtrigW<XfercfgSpec> {
664 SwtrigW::new(self, 2)
665 }
666 #[doc = "Bit 3 - Clear Trigger."]
667 #[inline(always)]
668 pub fn clrtrig(&mut self) -> ClrtrigW<XfercfgSpec> {
669 ClrtrigW::new(self, 3)
670 }
671 #[doc = "Bit 4 - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
672 #[inline(always)]
673 pub fn setinta(&mut self) -> SetintaW<XfercfgSpec> {
674 SetintaW::new(self, 4)
675 }
676 #[doc = "Bit 5 - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed."]
677 #[inline(always)]
678 pub fn setintb(&mut self) -> SetintbW<XfercfgSpec> {
679 SetintbW::new(self, 5)
680 }
681 #[doc = "Bits 8:9 - Transfer width used for this DMA channel."]
682 #[inline(always)]
683 pub fn width(&mut self) -> WidthW<XfercfgSpec> {
684 WidthW::new(self, 8)
685 }
686 #[doc = "Bits 12:13 - Determines whether the source address is incremented for each DMA transfer."]
687 #[inline(always)]
688 pub fn srcinc(&mut self) -> SrcincW<XfercfgSpec> {
689 SrcincW::new(self, 12)
690 }
691 #[doc = "Bits 14:15 - Determines whether the destination address is incremented for each DMA transfer."]
692 #[inline(always)]
693 pub fn dstinc(&mut self) -> DstincW<XfercfgSpec> {
694 DstincW::new(self, 14)
695 }
696 #[doc = "Bits 16:25 - Total number of transfers to be performed, minus 1 encoded. The number of bytes transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller uses this bit field during transfer to count down. Hence, it cannot be used by software to read back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of 1,024 transfers will be performed."]
697 #[inline(always)]
698 pub fn xfercount(&mut self) -> XfercountW<XfercfgSpec> {
699 XfercountW::new(self, 16)
700 }
701}
702#[doc = "Transfer configuration register for DMA channel .\n\nYou can [`read`](crate::Reg::read) this register and get [`xfercfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`xfercfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
703pub struct XfercfgSpec;
704impl crate::RegisterSpec for XfercfgSpec {
705 type Ux = u32;
706}
707#[doc = "`read()` method returns [`xfercfg::R`](R) reader structure"]
708impl crate::Readable for XfercfgSpec {}
709#[doc = "`write(|w| ..)` method takes [`xfercfg::W`](W) writer structure"]
710impl crate::Writable for XfercfgSpec {
711 type Safety = crate::Unsafe;
712 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
713 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
714}
715#[doc = "`reset()` method sets XFERCFG to value 0"]
716impl crate::Resettable for XfercfgSpec {
717 const RESET_VALUE: u32 = 0;
718}