mimxrt685s_pac/clkctl1/
dspmainramclkdiv.rs

1#[doc = "Register `DSPMAINRAMCLKDIV` reader"]
2pub type R = crate::R<DspmainramclkdivSpec>;
3#[doc = "Register `DSPMAINRAMCLKDIV` writer"]
4pub type W = crate::W<DspmainramclkdivSpec>;
5#[doc = "DSP MAINRAM Clock Ratio Control:\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Dspmramclkdiv {
10    #[doc = "0: DSP MAINRAM Clk = DSP Core CLK / 1."]
11    DspClkDivBy1 = 0,
12    #[doc = "1: DSP MAINRAM Clk = DSP Core CLK / 2."]
13    DspClkDivBy2 = 1,
14    #[doc = "2: DSP MAINRAM Clk = DSP Core CLK / 3."]
15    DspClkDivBy3 = 2,
16    #[doc = "3: DSP MAINRAM Clk = DSP Core CLK / 4."]
17    DspClkDivBy4 = 3,
18}
19impl From<Dspmramclkdiv> for u8 {
20    #[inline(always)]
21    fn from(variant: Dspmramclkdiv) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for Dspmramclkdiv {
26    type Ux = u8;
27}
28impl crate::IsEnum for Dspmramclkdiv {}
29#[doc = "Field `DSPMRAMCLKDIV` reader - DSP MAINRAM Clock Ratio Control:"]
30pub type DspmramclkdivR = crate::FieldReader<Dspmramclkdiv>;
31impl DspmramclkdivR {
32    #[doc = "Get enumerated values variant"]
33    #[inline(always)]
34    pub const fn variant(&self) -> Dspmramclkdiv {
35        match self.bits {
36            0 => Dspmramclkdiv::DspClkDivBy1,
37            1 => Dspmramclkdiv::DspClkDivBy2,
38            2 => Dspmramclkdiv::DspClkDivBy3,
39            3 => Dspmramclkdiv::DspClkDivBy4,
40            _ => unreachable!(),
41        }
42    }
43    #[doc = "DSP MAINRAM Clk = DSP Core CLK / 1."]
44    #[inline(always)]
45    pub fn is_dsp_clk_div_by_1(&self) -> bool {
46        *self == Dspmramclkdiv::DspClkDivBy1
47    }
48    #[doc = "DSP MAINRAM Clk = DSP Core CLK / 2."]
49    #[inline(always)]
50    pub fn is_dsp_clk_div_by_2(&self) -> bool {
51        *self == Dspmramclkdiv::DspClkDivBy2
52    }
53    #[doc = "DSP MAINRAM Clk = DSP Core CLK / 3."]
54    #[inline(always)]
55    pub fn is_dsp_clk_div_by_3(&self) -> bool {
56        *self == Dspmramclkdiv::DspClkDivBy3
57    }
58    #[doc = "DSP MAINRAM Clk = DSP Core CLK / 4."]
59    #[inline(always)]
60    pub fn is_dsp_clk_div_by_4(&self) -> bool {
61        *self == Dspmramclkdiv::DspClkDivBy4
62    }
63}
64#[doc = "Field `DSPMRAMCLKDIV` writer - DSP MAINRAM Clock Ratio Control:"]
65pub type DspmramclkdivW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dspmramclkdiv, crate::Safe>;
66impl<'a, REG> DspmramclkdivW<'a, REG>
67where
68    REG: crate::Writable + crate::RegisterSpec,
69    REG::Ux: From<u8>,
70{
71    #[doc = "DSP MAINRAM Clk = DSP Core CLK / 1."]
72    #[inline(always)]
73    pub fn dsp_clk_div_by_1(self) -> &'a mut crate::W<REG> {
74        self.variant(Dspmramclkdiv::DspClkDivBy1)
75    }
76    #[doc = "DSP MAINRAM Clk = DSP Core CLK / 2."]
77    #[inline(always)]
78    pub fn dsp_clk_div_by_2(self) -> &'a mut crate::W<REG> {
79        self.variant(Dspmramclkdiv::DspClkDivBy2)
80    }
81    #[doc = "DSP MAINRAM Clk = DSP Core CLK / 3."]
82    #[inline(always)]
83    pub fn dsp_clk_div_by_3(self) -> &'a mut crate::W<REG> {
84        self.variant(Dspmramclkdiv::DspClkDivBy3)
85    }
86    #[doc = "DSP MAINRAM Clk = DSP Core CLK / 4."]
87    #[inline(always)]
88    pub fn dsp_clk_div_by_4(self) -> &'a mut crate::W<REG> {
89        self.variant(Dspmramclkdiv::DspClkDivBy4)
90    }
91}
92impl R {
93    #[doc = "Bits 0:1 - DSP MAINRAM Clock Ratio Control:"]
94    #[inline(always)]
95    pub fn dspmramclkdiv(&self) -> DspmramclkdivR {
96        DspmramclkdivR::new((self.bits & 3) as u8)
97    }
98}
99#[cfg(feature = "debug")]
100impl core::fmt::Debug for R {
101    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
102        f.debug_struct("DSPMAINRAMCLKDIV")
103            .field("dspmramclkdiv", &self.dspmramclkdiv())
104            .finish()
105    }
106}
107impl W {
108    #[doc = "Bits 0:1 - DSP MAINRAM Clock Ratio Control:"]
109    #[inline(always)]
110    pub fn dspmramclkdiv(&mut self) -> DspmramclkdivW<DspmainramclkdivSpec> {
111        DspmramclkdivW::new(self, 0)
112    }
113}
114#[doc = "DSP main ram clock divider\n\nYou can [`read`](crate::Reg::read) this register and get [`dspmainramclkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dspmainramclkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
115pub struct DspmainramclkdivSpec;
116impl crate::RegisterSpec for DspmainramclkdivSpec {
117    type Ux = u32;
118}
119#[doc = "`read()` method returns [`dspmainramclkdiv::R`](R) reader structure"]
120impl crate::Readable for DspmainramclkdivSpec {}
121#[doc = "`write(|w| ..)` method takes [`dspmainramclkdiv::W`](W) writer structure"]
122impl crate::Writable for DspmainramclkdivSpec {
123    type Safety = crate::Unsafe;
124    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
125    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
126}
127#[doc = "`reset()` method sets DSPMAINRAMCLKDIV to value 0x01"]
128impl crate::Resettable for DspmainramclkdivSpec {
129    const RESET_VALUE: u32 = 0x01;
130}
mimxrt685s_pac/clkctl1/dspmainramclkdiv.rs

mimxrt685s_pac/clkctl1/
dspmainramclkdiv.rs
