mimxrt685s_pac/clkctl1/
ct32bitfclksel.rs

1#[doc = "Register `CT32BITFCLKSEL%s` reader"]
2pub type R = crate::R<Ct32bitfclkselSpec>;
3#[doc = "Register `CT32BITFCLKSEL%s` writer"]
4pub type W = crate::W<Ct32bitfclkselSpec>;
5#[doc = "CT32Bit Functional Clock Source Selection. . .\n\nValue on reset: 7"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Sel {
10    #[doc = "0: Main Clock."]
11    MainClk = 0,
12    #[doc = "1: SFRO Clock."]
13    SfroClk = 1,
14    #[doc = "2: FFRO Clock."]
15    FfroClk = 2,
16    #[doc = "3: Audio PLL Clock."]
17    AudioPllClk = 3,
18    #[doc = "4: Master Clock In."]
19    MasterClk = 4,
20    #[doc = "5: Low Power Oscillator Clock (LPOSC)."]
21    Lposc = 5,
22    #[doc = "7: None, this may be selected in order to reduce power when no output is needed."]
23    None = 7,
24}
25impl From<Sel> for u8 {
26    #[inline(always)]
27    fn from(variant: Sel) -> Self {
28        variant as _
29    }
30}
31impl crate::FieldSpec for Sel {
32    type Ux = u8;
33}
34impl crate::IsEnum for Sel {}
35#[doc = "Field `SEL` reader - CT32Bit Functional Clock Source Selection. . ."]
36pub type SelR = crate::FieldReader<Sel>;
37impl SelR {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<Sel> {
41        match self.bits {
42            0 => Some(Sel::MainClk),
43            1 => Some(Sel::SfroClk),
44            2 => Some(Sel::FfroClk),
45            3 => Some(Sel::AudioPllClk),
46            4 => Some(Sel::MasterClk),
47            5 => Some(Sel::Lposc),
48            7 => Some(Sel::None),
49            _ => None,
50        }
51    }
52    #[doc = "Main Clock."]
53    #[inline(always)]
54    pub fn is_main_clk(&self) -> bool {
55        *self == Sel::MainClk
56    }
57    #[doc = "SFRO Clock."]
58    #[inline(always)]
59    pub fn is_sfro_clk(&self) -> bool {
60        *self == Sel::SfroClk
61    }
62    #[doc = "FFRO Clock."]
63    #[inline(always)]
64    pub fn is_ffro_clk(&self) -> bool {
65        *self == Sel::FfroClk
66    }
67    #[doc = "Audio PLL Clock."]
68    #[inline(always)]
69    pub fn is_audio_pll_clk(&self) -> bool {
70        *self == Sel::AudioPllClk
71    }
72    #[doc = "Master Clock In."]
73    #[inline(always)]
74    pub fn is_master_clk(&self) -> bool {
75        *self == Sel::MasterClk
76    }
77    #[doc = "Low Power Oscillator Clock (LPOSC)."]
78    #[inline(always)]
79    pub fn is_lposc(&self) -> bool {
80        *self == Sel::Lposc
81    }
82    #[doc = "None, this may be selected in order to reduce power when no output is needed."]
83    #[inline(always)]
84    pub fn is_none(&self) -> bool {
85        *self == Sel::None
86    }
87}
88#[doc = "Field `SEL` writer - CT32Bit Functional Clock Source Selection. . ."]
89pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sel>;
90impl<'a, REG> SelW<'a, REG>
91where
92    REG: crate::Writable + crate::RegisterSpec,
93    REG::Ux: From<u8>,
94{
95    #[doc = "Main Clock."]
96    #[inline(always)]
97    pub fn main_clk(self) -> &'a mut crate::W<REG> {
98        self.variant(Sel::MainClk)
99    }
100    #[doc = "SFRO Clock."]
101    #[inline(always)]
102    pub fn sfro_clk(self) -> &'a mut crate::W<REG> {
103        self.variant(Sel::SfroClk)
104    }
105    #[doc = "FFRO Clock."]
106    #[inline(always)]
107    pub fn ffro_clk(self) -> &'a mut crate::W<REG> {
108        self.variant(Sel::FfroClk)
109    }
110    #[doc = "Audio PLL Clock."]
111    #[inline(always)]
112    pub fn audio_pll_clk(self) -> &'a mut crate::W<REG> {
113        self.variant(Sel::AudioPllClk)
114    }
115    #[doc = "Master Clock In."]
116    #[inline(always)]
117    pub fn master_clk(self) -> &'a mut crate::W<REG> {
118        self.variant(Sel::MasterClk)
119    }
120    #[doc = "Low Power Oscillator Clock (LPOSC)."]
121    #[inline(always)]
122    pub fn lposc(self) -> &'a mut crate::W<REG> {
123        self.variant(Sel::Lposc)
124    }
125    #[doc = "None, this may be selected in order to reduce power when no output is needed."]
126    #[inline(always)]
127    pub fn none(self) -> &'a mut crate::W<REG> {
128        self.variant(Sel::None)
129    }
130}
131impl R {
132    #[doc = "Bits 0:2 - CT32Bit Functional Clock Source Selection. . ."]
133    #[inline(always)]
134    pub fn sel(&self) -> SelR {
135        SelR::new((self.bits & 7) as u8)
136    }
137}
138#[cfg(feature = "debug")]
139impl core::fmt::Debug for R {
140    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
141        f.debug_struct("CT32BITFCLKSEL")
142            .field("sel", &self.sel())
143            .finish()
144    }
145}
146impl W {
147    #[doc = "Bits 0:2 - CT32Bit Functional Clock Source Selection. . ."]
148    #[inline(always)]
149    pub fn sel(&mut self) -> SelW<Ct32bitfclkselSpec> {
150        SelW::new(self, 0)
151    }
152}
153#[doc = "ct32bit timer N clock selection\n\nYou can [`read`](crate::Reg::read) this register and get [`ct32bitfclksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ct32bitfclksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
154pub struct Ct32bitfclkselSpec;
155impl crate::RegisterSpec for Ct32bitfclkselSpec {
156    type Ux = u32;
157}
158#[doc = "`read()` method returns [`ct32bitfclksel::R`](R) reader structure"]
159impl crate::Readable for Ct32bitfclkselSpec {}
160#[doc = "`write(|w| ..)` method takes [`ct32bitfclksel::W`](W) writer structure"]
161impl crate::Writable for Ct32bitfclkselSpec {
162    type Safety = crate::Unsafe;
163    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
164    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
165}
166#[doc = "`reset()` method sets CT32BITFCLKSEL%s to value 0x07"]
167impl crate::Resettable for Ct32bitfclkselSpec {
168    const RESET_VALUE: u32 = 0x07;
169}
mimxrt685s_pac/clkctl1/ct32bitfclksel.rs

mimxrt685s_pac/clkctl1/
ct32bitfclksel.rs
