mimxrt685s_pac/clkctl1/
clkoutsel1.rs1#[doc = "Register `CLKOUTSEL1` reader"]
2pub type R = crate::R<Clkoutsel1Spec>;
3#[doc = "Register `CLKOUTSEL1` writer"]
4pub type W = crate::W<Clkoutsel1Spec>;
5#[doc = "Clock out clock Source Selection. . .\n\nValue on reset: 7"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Sel {
10 #[doc = "0: CLKOUTSEL0 Multiplexed Output."]
11 Clkoutsel0Output = 0,
12 #[doc = "1: Main System PLL Clock."]
13 MainPllClk = 1,
14 #[doc = "2: SYSPLL0 AUX0_PLL_Clock."]
15 Syspll0Aux0PllClk = 2,
16 #[doc = "3: DSP PLL clock."]
17 DspPllClk = 3,
18 #[doc = "4: SYSPLL0 AUX1_PLL_Clock."]
19 Syspll0Aux1PllClk = 4,
20 #[doc = "5: AUDIO PLL Clock."]
21 AudioPllClk = 5,
22 #[doc = "6: 32KHz RTC Clock."]
23 RtcClk32khz = 6,
24 #[doc = "7: None, this may be selected in order to reduce power when no output is needed."]
25 None = 7,
26}
27impl From<Sel> for u8 {
28 #[inline(always)]
29 fn from(variant: Sel) -> Self {
30 variant as _
31 }
32}
33impl crate::FieldSpec for Sel {
34 type Ux = u8;
35}
36impl crate::IsEnum for Sel {}
37#[doc = "Field `SEL` reader - Clock out clock Source Selection. . ."]
38pub type SelR = crate::FieldReader<Sel>;
39impl SelR {
40 #[doc = "Get enumerated values variant"]
41 #[inline(always)]
42 pub const fn variant(&self) -> Sel {
43 match self.bits {
44 0 => Sel::Clkoutsel0Output,
45 1 => Sel::MainPllClk,
46 2 => Sel::Syspll0Aux0PllClk,
47 3 => Sel::DspPllClk,
48 4 => Sel::Syspll0Aux1PllClk,
49 5 => Sel::AudioPllClk,
50 6 => Sel::RtcClk32khz,
51 7 => Sel::None,
52 _ => unreachable!(),
53 }
54 }
55 #[doc = "CLKOUTSEL0 Multiplexed Output."]
56 #[inline(always)]
57 pub fn is_clkoutsel0_output(&self) -> bool {
58 *self == Sel::Clkoutsel0Output
59 }
60 #[doc = "Main System PLL Clock."]
61 #[inline(always)]
62 pub fn is_main_pll_clk(&self) -> bool {
63 *self == Sel::MainPllClk
64 }
65 #[doc = "SYSPLL0 AUX0_PLL_Clock."]
66 #[inline(always)]
67 pub fn is_syspll0_aux0_pll_clk(&self) -> bool {
68 *self == Sel::Syspll0Aux0PllClk
69 }
70 #[doc = "DSP PLL clock."]
71 #[inline(always)]
72 pub fn is_dsp_pll_clk(&self) -> bool {
73 *self == Sel::DspPllClk
74 }
75 #[doc = "SYSPLL0 AUX1_PLL_Clock."]
76 #[inline(always)]
77 pub fn is_syspll0_aux1_pll_clk(&self) -> bool {
78 *self == Sel::Syspll0Aux1PllClk
79 }
80 #[doc = "AUDIO PLL Clock."]
81 #[inline(always)]
82 pub fn is_audio_pll_clk(&self) -> bool {
83 *self == Sel::AudioPllClk
84 }
85 #[doc = "32KHz RTC Clock."]
86 #[inline(always)]
87 pub fn is_rtc_clk_32khz(&self) -> bool {
88 *self == Sel::RtcClk32khz
89 }
90 #[doc = "None, this may be selected in order to reduce power when no output is needed."]
91 #[inline(always)]
92 pub fn is_none(&self) -> bool {
93 *self == Sel::None
94 }
95}
96#[doc = "Field `SEL` writer - Clock out clock Source Selection. . ."]
97pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sel, crate::Safe>;
98impl<'a, REG> SelW<'a, REG>
99where
100 REG: crate::Writable + crate::RegisterSpec,
101 REG::Ux: From<u8>,
102{
103 #[doc = "CLKOUTSEL0 Multiplexed Output."]
104 #[inline(always)]
105 pub fn clkoutsel0_output(self) -> &'a mut crate::W<REG> {
106 self.variant(Sel::Clkoutsel0Output)
107 }
108 #[doc = "Main System PLL Clock."]
109 #[inline(always)]
110 pub fn main_pll_clk(self) -> &'a mut crate::W<REG> {
111 self.variant(Sel::MainPllClk)
112 }
113 #[doc = "SYSPLL0 AUX0_PLL_Clock."]
114 #[inline(always)]
115 pub fn syspll0_aux0_pll_clk(self) -> &'a mut crate::W<REG> {
116 self.variant(Sel::Syspll0Aux0PllClk)
117 }
118 #[doc = "DSP PLL clock."]
119 #[inline(always)]
120 pub fn dsp_pll_clk(self) -> &'a mut crate::W<REG> {
121 self.variant(Sel::DspPllClk)
122 }
123 #[doc = "SYSPLL0 AUX1_PLL_Clock."]
124 #[inline(always)]
125 pub fn syspll0_aux1_pll_clk(self) -> &'a mut crate::W<REG> {
126 self.variant(Sel::Syspll0Aux1PllClk)
127 }
128 #[doc = "AUDIO PLL Clock."]
129 #[inline(always)]
130 pub fn audio_pll_clk(self) -> &'a mut crate::W<REG> {
131 self.variant(Sel::AudioPllClk)
132 }
133 #[doc = "32KHz RTC Clock."]
134 #[inline(always)]
135 pub fn rtc_clk_32khz(self) -> &'a mut crate::W<REG> {
136 self.variant(Sel::RtcClk32khz)
137 }
138 #[doc = "None, this may be selected in order to reduce power when no output is needed."]
139 #[inline(always)]
140 pub fn none(self) -> &'a mut crate::W<REG> {
141 self.variant(Sel::None)
142 }
143}
144impl R {
145 #[doc = "Bits 0:2 - Clock out clock Source Selection. . ."]
146 #[inline(always)]
147 pub fn sel(&self) -> SelR {
148 SelR::new((self.bits & 7) as u8)
149 }
150}
151#[cfg(feature = "debug")]
152impl core::fmt::Debug for R {
153 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
154 f.debug_struct("CLKOUTSEL1")
155 .field("sel", &self.sel())
156 .finish()
157 }
158}
159impl W {
160 #[doc = "Bits 0:2 - Clock out clock Source Selection. . ."]
161 #[inline(always)]
162 pub fn sel(&mut self) -> SelW<Clkoutsel1Spec> {
163 SelW::new(self, 0)
164 }
165}
166#[doc = "clock out selection 1\n\nYou can [`read`](crate::Reg::read) this register and get [`clkoutsel1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkoutsel1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
167pub struct Clkoutsel1Spec;
168impl crate::RegisterSpec for Clkoutsel1Spec {
169 type Ux = u32;
170}
171#[doc = "`read()` method returns [`clkoutsel1::R`](R) reader structure"]
172impl crate::Readable for Clkoutsel1Spec {}
173#[doc = "`write(|w| ..)` method takes [`clkoutsel1::W`](W) writer structure"]
174impl crate::Writable for Clkoutsel1Spec {
175 type Safety = crate::Unsafe;
176 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
177 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
178}
179#[doc = "`reset()` method sets CLKOUTSEL1 to value 0x07"]
180impl crate::Resettable for Clkoutsel1Spec {
181 const RESET_VALUE: u32 = 0x07;
182}