mimxrt685s_pac/clkctl0/
sdio0fclksel.rs

1#[doc = "Register `SDIO0FCLKSEL` reader"]
2pub type R = crate::R<Sdio0fclkselSpec>;
3#[doc = "Register `SDIO0FCLKSEL` writer"]
4pub type W = crate::W<Sdio0fclkselSpec>;
5#[doc = "SDIO0 Functional Clock Source Selection. .\n\nValue on reset: 7"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Sel {
10    #[doc = "0: Main Clock."]
11    MainClk = 0,
12    #[doc = "1: Main System PLL Clock."]
13    MainSysPllClk = 1,
14    #[doc = "2: SYSPLL0 AUX0_PLL_Clock."]
15    Syspll0Aux0PllClock = 2,
16    #[doc = "3: FFRO Clock."]
17    FfroClk = 3,
18    #[doc = "4: SYSPLL0 AUX1_PLL_Clock."]
19    Syspll0Aux1PllClock = 4,
20    #[doc = "7: None, this may be selected in order to reduce power when no output is needed."]
21    None = 7,
22}
23impl From<Sel> for u8 {
24    #[inline(always)]
25    fn from(variant: Sel) -> Self {
26        variant as _
27    }
28}
29impl crate::FieldSpec for Sel {
30    type Ux = u8;
31}
32impl crate::IsEnum for Sel {}
33#[doc = "Field `SEL` reader - SDIO0 Functional Clock Source Selection. ."]
34pub type SelR = crate::FieldReader<Sel>;
35impl SelR {
36    #[doc = "Get enumerated values variant"]
37    #[inline(always)]
38    pub const fn variant(&self) -> Option<Sel> {
39        match self.bits {
40            0 => Some(Sel::MainClk),
41            1 => Some(Sel::MainSysPllClk),
42            2 => Some(Sel::Syspll0Aux0PllClock),
43            3 => Some(Sel::FfroClk),
44            4 => Some(Sel::Syspll0Aux1PllClock),
45            7 => Some(Sel::None),
46            _ => None,
47        }
48    }
49    #[doc = "Main Clock."]
50    #[inline(always)]
51    pub fn is_main_clk(&self) -> bool {
52        *self == Sel::MainClk
53    }
54    #[doc = "Main System PLL Clock."]
55    #[inline(always)]
56    pub fn is_main_sys_pll_clk(&self) -> bool {
57        *self == Sel::MainSysPllClk
58    }
59    #[doc = "SYSPLL0 AUX0_PLL_Clock."]
60    #[inline(always)]
61    pub fn is_syspll0_aux0_pll_clock(&self) -> bool {
62        *self == Sel::Syspll0Aux0PllClock
63    }
64    #[doc = "FFRO Clock."]
65    #[inline(always)]
66    pub fn is_ffro_clk(&self) -> bool {
67        *self == Sel::FfroClk
68    }
69    #[doc = "SYSPLL0 AUX1_PLL_Clock."]
70    #[inline(always)]
71    pub fn is_syspll0_aux1_pll_clock(&self) -> bool {
72        *self == Sel::Syspll0Aux1PllClock
73    }
74    #[doc = "None, this may be selected in order to reduce power when no output is needed."]
75    #[inline(always)]
76    pub fn is_none(&self) -> bool {
77        *self == Sel::None
78    }
79}
80#[doc = "Field `SEL` writer - SDIO0 Functional Clock Source Selection. ."]
81pub type SelW<'a, REG> = crate::FieldWriter<'a, REG, 3, Sel>;
82impl<'a, REG> SelW<'a, REG>
83where
84    REG: crate::Writable + crate::RegisterSpec,
85    REG::Ux: From<u8>,
86{
87    #[doc = "Main Clock."]
88    #[inline(always)]
89    pub fn main_clk(self) -> &'a mut crate::W<REG> {
90        self.variant(Sel::MainClk)
91    }
92    #[doc = "Main System PLL Clock."]
93    #[inline(always)]
94    pub fn main_sys_pll_clk(self) -> &'a mut crate::W<REG> {
95        self.variant(Sel::MainSysPllClk)
96    }
97    #[doc = "SYSPLL0 AUX0_PLL_Clock."]
98    #[inline(always)]
99    pub fn syspll0_aux0_pll_clock(self) -> &'a mut crate::W<REG> {
100        self.variant(Sel::Syspll0Aux0PllClock)
101    }
102    #[doc = "FFRO Clock."]
103    #[inline(always)]
104    pub fn ffro_clk(self) -> &'a mut crate::W<REG> {
105        self.variant(Sel::FfroClk)
106    }
107    #[doc = "SYSPLL0 AUX1_PLL_Clock."]
108    #[inline(always)]
109    pub fn syspll0_aux1_pll_clock(self) -> &'a mut crate::W<REG> {
110        self.variant(Sel::Syspll0Aux1PllClock)
111    }
112    #[doc = "None, this may be selected in order to reduce power when no output is needed."]
113    #[inline(always)]
114    pub fn none(self) -> &'a mut crate::W<REG> {
115        self.variant(Sel::None)
116    }
117}
118impl R {
119    #[doc = "Bits 0:2 - SDIO0 Functional Clock Source Selection. ."]
120    #[inline(always)]
121    pub fn sel(&self) -> SelR {
122        SelR::new((self.bits & 7) as u8)
123    }
124}
125#[cfg(feature = "debug")]
126impl core::fmt::Debug for R {
127    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
128        f.debug_struct("SDIO0FCLKSEL")
129            .field("sel", &self.sel())
130            .finish()
131    }
132}
133impl W {
134    #[doc = "Bits 0:2 - SDIO0 Functional Clock Source Selection. ."]
135    #[inline(always)]
136    pub fn sel(&mut self) -> SelW<Sdio0fclkselSpec> {
137        SelW::new(self, 0)
138    }
139}
140#[doc = "SDIO0 FCLK selection\n\nYou can [`read`](crate::Reg::read) this register and get [`sdio0fclksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdio0fclksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
141pub struct Sdio0fclkselSpec;
142impl crate::RegisterSpec for Sdio0fclkselSpec {
143    type Ux = u32;
144}
145#[doc = "`read()` method returns [`sdio0fclksel::R`](R) reader structure"]
146impl crate::Readable for Sdio0fclkselSpec {}
147#[doc = "`write(|w| ..)` method takes [`sdio0fclksel::W`](W) writer structure"]
148impl crate::Writable for Sdio0fclkselSpec {
149    type Safety = crate::Unsafe;
150    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
151    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
152}
153#[doc = "`reset()` method sets SDIO0FCLKSEL to value 0x07"]
154impl crate::Resettable for Sdio0fclkselSpec {
155    const RESET_VALUE: u32 = 0x07;
156}
mimxrt685s_pac/clkctl0/sdio0fclksel.rs

mimxrt685s_pac/clkctl0/
sdio0fclksel.rs
