1#[repr(C)]
2#[cfg_attr(feature = "debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 _reserved0: [u8; 0x10],
6 rom_mem_rule: [RomMemRule; 4],
7 _reserved1: [u8; 0x10],
8 flexspi0_region0_rule: [Flexspi0Region0Rule; 4],
9 flexspi0_region1_rule0: Flexspi0Region1Rule0,
10 _reserved3: [u8; 0x0c],
11 flexspi0_region2_rule0: Flexspi0Region2Rule0,
12 _reserved4: [u8; 0x0c],
13 flexspi0_region3_rule0: Flexspi0Region3Rule0,
14 _reserved5: [u8; 0x0c],
15 flexspi0_region4_rule0: Flexspi0Region4Rule0,
16 _reserved6: [u8; 0x1c],
17 ram00_rule: [Ram00Rule; 4],
18 ram01_rule: [Ram01Rule; 4],
19 _reserved8: [u8; 0x10],
20 ram02_rule: [Ram02Rule; 4],
21 ram03_rule: [Ram03Rule; 4],
22 _reserved10: [u8; 0x10],
23 ram04_rule: [Ram04Rule; 4],
24 ram05_rule: [Ram05Rule; 4],
25 ram06_rule: [Ram06Rule; 4],
26 ram07_rule: [Ram07Rule; 4],
27 _reserved14: [u8; 0x10],
28 ram08_rule: [Ram08Rule; 4],
29 ram09_rule: [Ram09Rule; 4],
30 ram10_rule: [Ram10Rule; 4],
31 ram11_rule: [Ram11Rule; 4],
32 _reserved18: [u8; 0x10],
33 ram12_rule: [Ram12Rule; 4],
34 ram13_rule: [Ram13Rule; 4],
35 ram14_rule: [Ram14Rule; 4],
36 ram15_rule: [Ram15Rule; 4],
37 _reserved22: [u8; 0x10],
38 ram16_rule: [Ram16Rule; 4],
39 ram17_rule: [Ram17Rule; 4],
40 ram18_rule: [Ram18Rule; 4],
41 ram19_rule: [Ram19Rule; 4],
42 _reserved26: [u8; 0x10],
43 ram20_rule: [Ram20Rule; 4],
44 ram21_rule: [Ram21Rule; 4],
45 ram22_rule: [Ram22Rule; 4],
46 ram23_rule: [Ram23Rule; 4],
47 _reserved30: [u8; 0x10],
48 ram24_rule: [Ram24Rule; 4],
49 ram25_rule: [Ram25Rule; 4],
50 ram26_rule: [Ram26Rule; 4],
51 ram27_rule: [Ram27Rule; 4],
52 _reserved34: [u8; 0x10],
53 ram28_rule: [Ram28Rule; 4],
54 ram29_rule: [Ram29Rule; 4],
55 _reserved36: [u8; 0x30],
56 pif_hifi4_x_mem_rule0: PifHifi4XMemRule0,
57 _reserved37: [u8; 0x1c],
58 apb_grp0_mem_rule0: ApbGrp0MemRule0,
59 apb_grp0_mem_rule1: ApbGrp0MemRule1,
60 _reserved39: [u8; 0x08],
61 apb_grp1_mem_rule0: ApbGrp1MemRule0,
62 apb_grp1_mem_rule1: ApbGrp1MemRule1,
63 apb_grp1_mem_rule2: ApbGrp1MemRule2,
64 _reserved42: [u8; 0x04],
65 ahb_periph0_slave_rule0: AhbPeriph0SlaveRule0,
66 _reserved43: [u8; 0x0c],
67 aips_bridge0_mem_rule0: AipsBridge0MemRule0,
68 _reserved44: [u8; 0x0c],
69 ahb_periph1_slave_rule0: AhbPeriph1SlaveRule0,
70 _reserved45: [u8; 0x1c],
71 aips_bridge1_mem_rule0: AipsBridge1MemRule0,
72 aips_bridge1_mem_rule1: AipsBridge1MemRule1,
73 _reserved47: [u8; 0x08],
74 ahb_periph2_slave_rule0: AhbPeriph2SlaveRule0,
75 _reserved48: [u8; 0x0c],
76 security_ctrl_mem_rule0: SecurityCtrlMemRule0,
77 _reserved49: [u8; 0x0c],
78 ahb_periph3_slave_rule0: AhbPeriph3SlaveRule0,
79 _reserved50: [u8; 0x0a2c],
80 sec_vio_addr: [SecVioAddr; 18],
81 _reserved51: [u8; 0x38],
82 sec_vio_misc_info: [SecVioMiscInfo; 18],
83 _reserved52: [u8; 0x38],
84 sec_vio_info_valid: SecVioInfoValid,
85 _reserved53: [u8; 0x7c],
86 sec_gpio_mask0: SecGpioMask0,
87 sec_gpio_mask1: SecGpioMask1,
88 sec_gpio_mask2: SecGpioMask2,
89 sec_gpio_mask3: SecGpioMask3,
90 sec_gpio_mask4: SecGpioMask4,
91 sec_gpio_mask5: SecGpioMask5,
92 sec_gpio_mask6: SecGpioMask6,
93 sec_gpio_mask7: SecGpioMask7,
94 sec_dsp_int_mask: SecDspIntMask,
95 _reserved62: [u8; 0x18],
96 sec_mask_lock: SecMaskLock,
97 _reserved63: [u8; 0x10],
98 master_sec_level: MasterSecLevel,
99 master_sec_level_anti_pol: MasterSecLevelAntiPol,
100 _reserved65: [u8; 0x14],
101 cm33_lock_reg: Cm33LockReg,
102 _reserved66: [u8; 0x08],
103 misc_ctrl_dp_reg: MiscCtrlDpReg,
104 misc_ctrl_reg: MiscCtrlReg,
105}
106impl RegisterBlock {
107 #[doc = "0x10..0x20 - Memory ROM Rule(n) Register"]
108 #[inline(always)]
109 pub const fn rom_mem_rule(&self, n: usize) -> &RomMemRule {
110 &self.rom_mem_rule[n]
111 }
112 #[doc = "Iterator for array of:"]
113 #[doc = "0x10..0x20 - Memory ROM Rule(n) Register"]
114 #[inline(always)]
115 pub fn rom_mem_rule_iter(&self) -> impl Iterator<Item = &RomMemRule> {
116 self.rom_mem_rule.iter()
117 }
118 #[doc = "0x30..0x40 - FLEXSPI0 Region 0 Rule(n) Register"]
119 #[inline(always)]
120 pub const fn flexspi0_region0_rule(&self, n: usize) -> &Flexspi0Region0Rule {
121 &self.flexspi0_region0_rule[n]
122 }
123 #[doc = "Iterator for array of:"]
124 #[doc = "0x30..0x40 - FLEXSPI0 Region 0 Rule(n) Register"]
125 #[inline(always)]
126 pub fn flexspi0_region0_rule_iter(&self) -> impl Iterator<Item = &Flexspi0Region0Rule> {
127 self.flexspi0_region0_rule.iter()
128 }
129 #[doc = "0x40 - FLEXSPI0 Region 1 Rule 0 Register"]
130 #[inline(always)]
131 pub const fn flexspi0_region1_rule0(&self) -> &Flexspi0Region1Rule0 {
132 &self.flexspi0_region1_rule0
133 }
134 #[doc = "0x50 - FLEXSPI0 Region 2 Rule 0 Register"]
135 #[inline(always)]
136 pub const fn flexspi0_region2_rule0(&self) -> &Flexspi0Region2Rule0 {
137 &self.flexspi0_region2_rule0
138 }
139 #[doc = "0x60 - FLEXSPI0 Region 3 Rule 0 Register"]
140 #[inline(always)]
141 pub const fn flexspi0_region3_rule0(&self) -> &Flexspi0Region3Rule0 {
142 &self.flexspi0_region3_rule0
143 }
144 #[doc = "0x70 - FLEXSPI0 Region 4 Rule 0 Register"]
145 #[inline(always)]
146 pub const fn flexspi0_region4_rule0(&self) -> &Flexspi0Region4Rule0 {
147 &self.flexspi0_region4_rule0
148 }
149 #[doc = "0x90..0xa0 - SRAM Partition 00 Rule(n) Register"]
150 #[inline(always)]
151 pub const fn ram00_rule(&self, n: usize) -> &Ram00Rule {
152 &self.ram00_rule[n]
153 }
154 #[doc = "Iterator for array of:"]
155 #[doc = "0x90..0xa0 - SRAM Partition 00 Rule(n) Register"]
156 #[inline(always)]
157 pub fn ram00_rule_iter(&self) -> impl Iterator<Item = &Ram00Rule> {
158 self.ram00_rule.iter()
159 }
160 #[doc = "0xa0..0xb0 - SRAM Partition 01 Rule(n) Register"]
161 #[inline(always)]
162 pub const fn ram01_rule(&self, n: usize) -> &Ram01Rule {
163 &self.ram01_rule[n]
164 }
165 #[doc = "Iterator for array of:"]
166 #[doc = "0xa0..0xb0 - SRAM Partition 01 Rule(n) Register"]
167 #[inline(always)]
168 pub fn ram01_rule_iter(&self) -> impl Iterator<Item = &Ram01Rule> {
169 self.ram01_rule.iter()
170 }
171 #[doc = "0xc0..0xd0 - SRAM Partition 02 Rule(n) Register"]
172 #[inline(always)]
173 pub const fn ram02_rule(&self, n: usize) -> &Ram02Rule {
174 &self.ram02_rule[n]
175 }
176 #[doc = "Iterator for array of:"]
177 #[doc = "0xc0..0xd0 - SRAM Partition 02 Rule(n) Register"]
178 #[inline(always)]
179 pub fn ram02_rule_iter(&self) -> impl Iterator<Item = &Ram02Rule> {
180 self.ram02_rule.iter()
181 }
182 #[doc = "0xd0..0xe0 - SRAM Partition 03 Rule(n) Register"]
183 #[inline(always)]
184 pub const fn ram03_rule(&self, n: usize) -> &Ram03Rule {
185 &self.ram03_rule[n]
186 }
187 #[doc = "Iterator for array of:"]
188 #[doc = "0xd0..0xe0 - SRAM Partition 03 Rule(n) Register"]
189 #[inline(always)]
190 pub fn ram03_rule_iter(&self) -> impl Iterator<Item = &Ram03Rule> {
191 self.ram03_rule.iter()
192 }
193 #[doc = "0xf0..0x100 - SRAM Partition 04 Rule(n) Register"]
194 #[inline(always)]
195 pub const fn ram04_rule(&self, n: usize) -> &Ram04Rule {
196 &self.ram04_rule[n]
197 }
198 #[doc = "Iterator for array of:"]
199 #[doc = "0xf0..0x100 - SRAM Partition 04 Rule(n) Register"]
200 #[inline(always)]
201 pub fn ram04_rule_iter(&self) -> impl Iterator<Item = &Ram04Rule> {
202 self.ram04_rule.iter()
203 }
204 #[doc = "0x100..0x110 - SRAM Partition 05 Rule(n) Register"]
205 #[inline(always)]
206 pub const fn ram05_rule(&self, n: usize) -> &Ram05Rule {
207 &self.ram05_rule[n]
208 }
209 #[doc = "Iterator for array of:"]
210 #[doc = "0x100..0x110 - SRAM Partition 05 Rule(n) Register"]
211 #[inline(always)]
212 pub fn ram05_rule_iter(&self) -> impl Iterator<Item = &Ram05Rule> {
213 self.ram05_rule.iter()
214 }
215 #[doc = "0x110..0x120 - SRAM Partition 06 Rule(n) Register"]
216 #[inline(always)]
217 pub const fn ram06_rule(&self, n: usize) -> &Ram06Rule {
218 &self.ram06_rule[n]
219 }
220 #[doc = "Iterator for array of:"]
221 #[doc = "0x110..0x120 - SRAM Partition 06 Rule(n) Register"]
222 #[inline(always)]
223 pub fn ram06_rule_iter(&self) -> impl Iterator<Item = &Ram06Rule> {
224 self.ram06_rule.iter()
225 }
226 #[doc = "0x120..0x130 - SRAM Partition 07 Rule(n) Register"]
227 #[inline(always)]
228 pub const fn ram07_rule(&self, n: usize) -> &Ram07Rule {
229 &self.ram07_rule[n]
230 }
231 #[doc = "Iterator for array of:"]
232 #[doc = "0x120..0x130 - SRAM Partition 07 Rule(n) Register"]
233 #[inline(always)]
234 pub fn ram07_rule_iter(&self) -> impl Iterator<Item = &Ram07Rule> {
235 self.ram07_rule.iter()
236 }
237 #[doc = "0x140..0x150 - SRAM Partition 08 Rule(n) Register"]
238 #[inline(always)]
239 pub const fn ram08_rule(&self, n: usize) -> &Ram08Rule {
240 &self.ram08_rule[n]
241 }
242 #[doc = "Iterator for array of:"]
243 #[doc = "0x140..0x150 - SRAM Partition 08 Rule(n) Register"]
244 #[inline(always)]
245 pub fn ram08_rule_iter(&self) -> impl Iterator<Item = &Ram08Rule> {
246 self.ram08_rule.iter()
247 }
248 #[doc = "0x150..0x160 - SRAM Partition 09 Rule(n) Register"]
249 #[inline(always)]
250 pub const fn ram09_rule(&self, n: usize) -> &Ram09Rule {
251 &self.ram09_rule[n]
252 }
253 #[doc = "Iterator for array of:"]
254 #[doc = "0x150..0x160 - SRAM Partition 09 Rule(n) Register"]
255 #[inline(always)]
256 pub fn ram09_rule_iter(&self) -> impl Iterator<Item = &Ram09Rule> {
257 self.ram09_rule.iter()
258 }
259 #[doc = "0x160..0x170 - SRAM Partition 10 Rule(n) Register"]
260 #[inline(always)]
261 pub const fn ram10_rule(&self, n: usize) -> &Ram10Rule {
262 &self.ram10_rule[n]
263 }
264 #[doc = "Iterator for array of:"]
265 #[doc = "0x160..0x170 - SRAM Partition 10 Rule(n) Register"]
266 #[inline(always)]
267 pub fn ram10_rule_iter(&self) -> impl Iterator<Item = &Ram10Rule> {
268 self.ram10_rule.iter()
269 }
270 #[doc = "0x170..0x180 - SRAM Partition 11 Rule(n) Register"]
271 #[inline(always)]
272 pub const fn ram11_rule(&self, n: usize) -> &Ram11Rule {
273 &self.ram11_rule[n]
274 }
275 #[doc = "Iterator for array of:"]
276 #[doc = "0x170..0x180 - SRAM Partition 11 Rule(n) Register"]
277 #[inline(always)]
278 pub fn ram11_rule_iter(&self) -> impl Iterator<Item = &Ram11Rule> {
279 self.ram11_rule.iter()
280 }
281 #[doc = "0x190..0x1a0 - SRAM Partition 12 Rule(n) Register"]
282 #[inline(always)]
283 pub const fn ram12_rule(&self, n: usize) -> &Ram12Rule {
284 &self.ram12_rule[n]
285 }
286 #[doc = "Iterator for array of:"]
287 #[doc = "0x190..0x1a0 - SRAM Partition 12 Rule(n) Register"]
288 #[inline(always)]
289 pub fn ram12_rule_iter(&self) -> impl Iterator<Item = &Ram12Rule> {
290 self.ram12_rule.iter()
291 }
292 #[doc = "0x1a0..0x1b0 - SRAM Partition 13 Rule(n) Register"]
293 #[inline(always)]
294 pub const fn ram13_rule(&self, n: usize) -> &Ram13Rule {
295 &self.ram13_rule[n]
296 }
297 #[doc = "Iterator for array of:"]
298 #[doc = "0x1a0..0x1b0 - SRAM Partition 13 Rule(n) Register"]
299 #[inline(always)]
300 pub fn ram13_rule_iter(&self) -> impl Iterator<Item = &Ram13Rule> {
301 self.ram13_rule.iter()
302 }
303 #[doc = "0x1b0..0x1c0 - SRAM Partition 14 Rule(n) Register"]
304 #[inline(always)]
305 pub const fn ram14_rule(&self, n: usize) -> &Ram14Rule {
306 &self.ram14_rule[n]
307 }
308 #[doc = "Iterator for array of:"]
309 #[doc = "0x1b0..0x1c0 - SRAM Partition 14 Rule(n) Register"]
310 #[inline(always)]
311 pub fn ram14_rule_iter(&self) -> impl Iterator<Item = &Ram14Rule> {
312 self.ram14_rule.iter()
313 }
314 #[doc = "0x1c0..0x1d0 - SRAM Partition 15 Rule(n) Register"]
315 #[inline(always)]
316 pub const fn ram15_rule(&self, n: usize) -> &Ram15Rule {
317 &self.ram15_rule[n]
318 }
319 #[doc = "Iterator for array of:"]
320 #[doc = "0x1c0..0x1d0 - SRAM Partition 15 Rule(n) Register"]
321 #[inline(always)]
322 pub fn ram15_rule_iter(&self) -> impl Iterator<Item = &Ram15Rule> {
323 self.ram15_rule.iter()
324 }
325 #[doc = "0x1e0..0x1f0 - SRAM Partition 16 Rule(n) Register"]
326 #[inline(always)]
327 pub const fn ram16_rule(&self, n: usize) -> &Ram16Rule {
328 &self.ram16_rule[n]
329 }
330 #[doc = "Iterator for array of:"]
331 #[doc = "0x1e0..0x1f0 - SRAM Partition 16 Rule(n) Register"]
332 #[inline(always)]
333 pub fn ram16_rule_iter(&self) -> impl Iterator<Item = &Ram16Rule> {
334 self.ram16_rule.iter()
335 }
336 #[doc = "0x1f0..0x200 - SRAM Partition 17 Rule(n) Register"]
337 #[inline(always)]
338 pub const fn ram17_rule(&self, n: usize) -> &Ram17Rule {
339 &self.ram17_rule[n]
340 }
341 #[doc = "Iterator for array of:"]
342 #[doc = "0x1f0..0x200 - SRAM Partition 17 Rule(n) Register"]
343 #[inline(always)]
344 pub fn ram17_rule_iter(&self) -> impl Iterator<Item = &Ram17Rule> {
345 self.ram17_rule.iter()
346 }
347 #[doc = "0x200..0x210 - SRAM Partition 18 Rule(n) Register"]
348 #[inline(always)]
349 pub const fn ram18_rule(&self, n: usize) -> &Ram18Rule {
350 &self.ram18_rule[n]
351 }
352 #[doc = "Iterator for array of:"]
353 #[doc = "0x200..0x210 - SRAM Partition 18 Rule(n) Register"]
354 #[inline(always)]
355 pub fn ram18_rule_iter(&self) -> impl Iterator<Item = &Ram18Rule> {
356 self.ram18_rule.iter()
357 }
358 #[doc = "0x210..0x220 - SRAM Partition 19 Rule(n) Register"]
359 #[inline(always)]
360 pub const fn ram19_rule(&self, n: usize) -> &Ram19Rule {
361 &self.ram19_rule[n]
362 }
363 #[doc = "Iterator for array of:"]
364 #[doc = "0x210..0x220 - SRAM Partition 19 Rule(n) Register"]
365 #[inline(always)]
366 pub fn ram19_rule_iter(&self) -> impl Iterator<Item = &Ram19Rule> {
367 self.ram19_rule.iter()
368 }
369 #[doc = "0x230..0x240 - SRAM Partition 20 Rule(n) Register"]
370 #[inline(always)]
371 pub const fn ram20_rule(&self, n: usize) -> &Ram20Rule {
372 &self.ram20_rule[n]
373 }
374 #[doc = "Iterator for array of:"]
375 #[doc = "0x230..0x240 - SRAM Partition 20 Rule(n) Register"]
376 #[inline(always)]
377 pub fn ram20_rule_iter(&self) -> impl Iterator<Item = &Ram20Rule> {
378 self.ram20_rule.iter()
379 }
380 #[doc = "0x240..0x250 - SRAM Partition 21 Rule(n) Register"]
381 #[inline(always)]
382 pub const fn ram21_rule(&self, n: usize) -> &Ram21Rule {
383 &self.ram21_rule[n]
384 }
385 #[doc = "Iterator for array of:"]
386 #[doc = "0x240..0x250 - SRAM Partition 21 Rule(n) Register"]
387 #[inline(always)]
388 pub fn ram21_rule_iter(&self) -> impl Iterator<Item = &Ram21Rule> {
389 self.ram21_rule.iter()
390 }
391 #[doc = "0x250..0x260 - SRAM Partition 22 Rule(n) Register"]
392 #[inline(always)]
393 pub const fn ram22_rule(&self, n: usize) -> &Ram22Rule {
394 &self.ram22_rule[n]
395 }
396 #[doc = "Iterator for array of:"]
397 #[doc = "0x250..0x260 - SRAM Partition 22 Rule(n) Register"]
398 #[inline(always)]
399 pub fn ram22_rule_iter(&self) -> impl Iterator<Item = &Ram22Rule> {
400 self.ram22_rule.iter()
401 }
402 #[doc = "0x260..0x270 - SRAM Partition 23 Rule(n) Register"]
403 #[inline(always)]
404 pub const fn ram23_rule(&self, n: usize) -> &Ram23Rule {
405 &self.ram23_rule[n]
406 }
407 #[doc = "Iterator for array of:"]
408 #[doc = "0x260..0x270 - SRAM Partition 23 Rule(n) Register"]
409 #[inline(always)]
410 pub fn ram23_rule_iter(&self) -> impl Iterator<Item = &Ram23Rule> {
411 self.ram23_rule.iter()
412 }
413 #[doc = "0x280..0x290 - SRAM Partition 24 Rule(n) Register"]
414 #[inline(always)]
415 pub const fn ram24_rule(&self, n: usize) -> &Ram24Rule {
416 &self.ram24_rule[n]
417 }
418 #[doc = "Iterator for array of:"]
419 #[doc = "0x280..0x290 - SRAM Partition 24 Rule(n) Register"]
420 #[inline(always)]
421 pub fn ram24_rule_iter(&self) -> impl Iterator<Item = &Ram24Rule> {
422 self.ram24_rule.iter()
423 }
424 #[doc = "0x290..0x2a0 - SRAM Partition 25 Rule(n) Register"]
425 #[inline(always)]
426 pub const fn ram25_rule(&self, n: usize) -> &Ram25Rule {
427 &self.ram25_rule[n]
428 }
429 #[doc = "Iterator for array of:"]
430 #[doc = "0x290..0x2a0 - SRAM Partition 25 Rule(n) Register"]
431 #[inline(always)]
432 pub fn ram25_rule_iter(&self) -> impl Iterator<Item = &Ram25Rule> {
433 self.ram25_rule.iter()
434 }
435 #[doc = "0x2a0..0x2b0 - SRAM Partition 26 Rule(n) Register"]
436 #[inline(always)]
437 pub const fn ram26_rule(&self, n: usize) -> &Ram26Rule {
438 &self.ram26_rule[n]
439 }
440 #[doc = "Iterator for array of:"]
441 #[doc = "0x2a0..0x2b0 - SRAM Partition 26 Rule(n) Register"]
442 #[inline(always)]
443 pub fn ram26_rule_iter(&self) -> impl Iterator<Item = &Ram26Rule> {
444 self.ram26_rule.iter()
445 }
446 #[doc = "0x2b0..0x2c0 - SRAM Partition 27 Rule(n) Register"]
447 #[inline(always)]
448 pub const fn ram27_rule(&self, n: usize) -> &Ram27Rule {
449 &self.ram27_rule[n]
450 }
451 #[doc = "Iterator for array of:"]
452 #[doc = "0x2b0..0x2c0 - SRAM Partition 27 Rule(n) Register"]
453 #[inline(always)]
454 pub fn ram27_rule_iter(&self) -> impl Iterator<Item = &Ram27Rule> {
455 self.ram27_rule.iter()
456 }
457 #[doc = "0x2d0..0x2e0 - SRAM Partition 28 Rule(n) Register"]
458 #[inline(always)]
459 pub const fn ram28_rule(&self, n: usize) -> &Ram28Rule {
460 &self.ram28_rule[n]
461 }
462 #[doc = "Iterator for array of:"]
463 #[doc = "0x2d0..0x2e0 - SRAM Partition 28 Rule(n) Register"]
464 #[inline(always)]
465 pub fn ram28_rule_iter(&self) -> impl Iterator<Item = &Ram28Rule> {
466 self.ram28_rule.iter()
467 }
468 #[doc = "0x2e0..0x2f0 - SRAM Partition 29 Rule(n) Register"]
469 #[inline(always)]
470 pub const fn ram29_rule(&self, n: usize) -> &Ram29Rule {
471 &self.ram29_rule[n]
472 }
473 #[doc = "Iterator for array of:"]
474 #[doc = "0x2e0..0x2f0 - SRAM Partition 29 Rule(n) Register"]
475 #[inline(always)]
476 pub fn ram29_rule_iter(&self) -> impl Iterator<Item = &Ram29Rule> {
477 self.ram29_rule.iter()
478 }
479 #[doc = "0x320 - Security access rules for HiFi 4 memory sectors (0x24000000--0x240FFFFF). Each sector is 32 Kbytes, there're 4 sectors in total."]
480 #[inline(always)]
481 pub const fn pif_hifi4_x_mem_rule0(&self) -> &PifHifi4XMemRule0 {
482 &self.pif_hifi4_x_mem_rule0
483 }
484 #[doc = "0x340 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total."]
485 #[inline(always)]
486 pub const fn apb_grp0_mem_rule0(&self) -> &ApbGrp0MemRule0 {
487 &self.apb_grp0_mem_rule0
488 }
489 #[doc = "0x344 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total."]
490 #[inline(always)]
491 pub const fn apb_grp0_mem_rule1(&self) -> &ApbGrp0MemRule1 {
492 &self.apb_grp0_mem_rule1
493 }
494 #[doc = "0x350 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total."]
495 #[inline(always)]
496 pub const fn apb_grp1_mem_rule0(&self) -> &ApbGrp1MemRule0 {
497 &self.apb_grp1_mem_rule0
498 }
499 #[doc = "0x354 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total."]
500 #[inline(always)]
501 pub const fn apb_grp1_mem_rule1(&self) -> &ApbGrp1MemRule1 {
502 &self.apb_grp1_mem_rule1
503 }
504 #[doc = "0x358 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total."]
505 #[inline(always)]
506 pub const fn apb_grp1_mem_rule2(&self) -> &ApbGrp1MemRule2 {
507 &self.apb_grp1_mem_rule2
508 }
509 #[doc = "0x360 - Security access rules for AHB peripheral slaves area 0x40100000--0x4010FFFF"]
510 #[inline(always)]
511 pub const fn ahb_periph0_slave_rule0(&self) -> &AhbPeriph0SlaveRule0 {
512 &self.ahb_periph0_slave_rule0
513 }
514 #[doc = "0x370 - 0x40110000--0x4011FFFF"]
515 #[inline(always)]
516 pub const fn aips_bridge0_mem_rule0(&self) -> &AipsBridge0MemRule0 {
517 &self.aips_bridge0_mem_rule0
518 }
519 #[doc = "0x380 - the memory map is 0x40120000--0x40127FFF"]
520 #[inline(always)]
521 pub const fn ahb_periph1_slave_rule0(&self) -> &AhbPeriph1SlaveRule0 {
522 &self.ahb_periph1_slave_rule0
523 }
524 #[doc = "0x3a0 - Security access rules for AIPS Bridge peripherals. Each AIPS bridge sector is 4 Kbytes, there're 16 sectors in total."]
525 #[inline(always)]
526 pub const fn aips_bridge1_mem_rule0(&self) -> &AipsBridge1MemRule0 {
527 &self.aips_bridge1_mem_rule0
528 }
529 #[doc = "0x3a4 - Security access rules for AIPS Bridge peripherals. Each AIPS bridge sector is 4 Kbytes, there're 16 sectors in total."]
530 #[inline(always)]
531 pub const fn aips_bridge1_mem_rule1(&self) -> &AipsBridge1MemRule1 {
532 &self.aips_bridge1_mem_rule1
533 }
534 #[doc = "0x3b0 - Security access rules for AHB peripheral slaves area 0x40140000--0x4014BFFF"]
535 #[inline(always)]
536 pub const fn ahb_periph2_slave_rule0(&self) -> &AhbPeriph2SlaveRule0 {
537 &self.ahb_periph2_slave_rule0
538 }
539 #[doc = "0x3c0 - 0x40148000--0x4014BFFF"]
540 #[inline(always)]
541 pub const fn security_ctrl_mem_rule0(&self) -> &SecurityCtrlMemRule0 {
542 &self.security_ctrl_mem_rule0
543 }
544 #[doc = "0x3d0 - Security access rules for AHB peripheral slaves area 0x40150000--0x40158FFF"]
545 #[inline(always)]
546 pub const fn ahb_periph3_slave_rule0(&self) -> &AhbPeriph3SlaveRule0 {
547 &self.ahb_periph3_slave_rule0
548 }
549 #[doc = "0xe00..0xe48 - most recent security violation address for AHB layer n"]
550 #[inline(always)]
551 pub const fn sec_vio_addr(&self, n: usize) -> &SecVioAddr {
552 &self.sec_vio_addr[n]
553 }
554 #[doc = "Iterator for array of:"]
555 #[doc = "0xe00..0xe48 - most recent security violation address for AHB layer n"]
556 #[inline(always)]
557 pub fn sec_vio_addr_iter(&self) -> impl Iterator<Item = &SecVioAddr> {
558 self.sec_vio_addr.iter()
559 }
560 #[doc = "0xe80..0xec8 - most recent security violation miscellaneous information for AHB layer n"]
561 #[inline(always)]
562 pub const fn sec_vio_misc_info(&self, n: usize) -> &SecVioMiscInfo {
563 &self.sec_vio_misc_info[n]
564 }
565 #[doc = "Iterator for array of:"]
566 #[doc = "0xe80..0xec8 - most recent security violation miscellaneous information for AHB layer n"]
567 #[inline(always)]
568 pub fn sec_vio_misc_info_iter(&self) -> impl Iterator<Item = &SecVioMiscInfo> {
569 self.sec_vio_misc_info.iter()
570 }
571 #[doc = "0xf00 - security violation address/information registers valid flags"]
572 #[inline(always)]
573 pub const fn sec_vio_info_valid(&self) -> &SecVioInfoValid {
574 &self.sec_vio_info_valid
575 }
576 #[doc = "0xf80 - Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world."]
577 #[inline(always)]
578 pub const fn sec_gpio_mask0(&self) -> &SecGpioMask0 {
579 &self.sec_gpio_mask0
580 }
581 #[doc = "0xf84 - Secure GPIO mask for port 1 pins."]
582 #[inline(always)]
583 pub const fn sec_gpio_mask1(&self) -> &SecGpioMask1 {
584 &self.sec_gpio_mask1
585 }
586 #[doc = "0xf88 - Secure GPIO mask for port 2 pins."]
587 #[inline(always)]
588 pub const fn sec_gpio_mask2(&self) -> &SecGpioMask2 {
589 &self.sec_gpio_mask2
590 }
591 #[doc = "0xf8c - Secure GPIO mask for port 3 pins."]
592 #[inline(always)]
593 pub const fn sec_gpio_mask3(&self) -> &SecGpioMask3 {
594 &self.sec_gpio_mask3
595 }
596 #[doc = "0xf90 - Secure GPIO mask for port 4 pins."]
597 #[inline(always)]
598 pub const fn sec_gpio_mask4(&self) -> &SecGpioMask4 {
599 &self.sec_gpio_mask4
600 }
601 #[doc = "0xf94 - Secure GPIO mask for port 5 pins."]
602 #[inline(always)]
603 pub const fn sec_gpio_mask5(&self) -> &SecGpioMask5 {
604 &self.sec_gpio_mask5
605 }
606 #[doc = "0xf98 - Secure GPIO mask for port 6 pins."]
607 #[inline(always)]
608 pub const fn sec_gpio_mask6(&self) -> &SecGpioMask6 {
609 &self.sec_gpio_mask6
610 }
611 #[doc = "0xf9c - Secure GPIO mask for port 7 pins."]
612 #[inline(always)]
613 pub const fn sec_gpio_mask7(&self) -> &SecGpioMask7 {
614 &self.sec_gpio_mask7
615 }
616 #[doc = "0xfa0 - secure general purpose register 8 used to mask interrupts to DSP for security purpose"]
617 #[inline(always)]
618 pub const fn sec_dsp_int_mask(&self) -> &SecDspIntMask {
619 &self.sec_dsp_int_mask
620 }
621 #[doc = "0xfbc - sec_gp_reg write-lock bits"]
622 #[inline(always)]
623 pub const fn sec_mask_lock(&self) -> &SecMaskLock {
624 &self.sec_mask_lock
625 }
626 #[doc = "0xfd0 - master secure level register"]
627 #[inline(always)]
628 pub const fn master_sec_level(&self) -> &MasterSecLevel {
629 &self.master_sec_level
630 }
631 #[doc = "0xfd4 - master secure level anti-pole register"]
632 #[inline(always)]
633 pub const fn master_sec_level_anti_pol(&self) -> &MasterSecLevelAntiPol {
634 &self.master_sec_level_anti_pol
635 }
636 #[doc = "0xfec - m33 lock control register"]
637 #[inline(always)]
638 pub const fn cm33_lock_reg(&self) -> &Cm33LockReg {
639 &self.cm33_lock_reg
640 }
641 #[doc = "0xff8 - secure control duplicate register"]
642 #[inline(always)]
643 pub const fn misc_ctrl_dp_reg(&self) -> &MiscCtrlDpReg {
644 &self.misc_ctrl_dp_reg
645 }
646 #[doc = "0xffc - secure control register"]
647 #[inline(always)]
648 pub const fn misc_ctrl_reg(&self) -> &MiscCtrlReg {
649 &self.misc_ctrl_reg
650 }
651}
652#[doc = "ROM_MEM_RULE (rw) register accessor: Memory ROM Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rom_mem_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rom_mem_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rom_mem_rule`]
653module"]
654#[doc(alias = "ROM_MEM_RULE")]
655pub type RomMemRule = crate::Reg<rom_mem_rule::RomMemRuleSpec>;
656#[doc = "Memory ROM Rule(n) Register"]
657pub mod rom_mem_rule;
658#[doc = "FLEXSPI0_REGION0_RULE (rw) register accessor: FLEXSPI0 Region 0 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flexspi0_region0_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flexspi0_region0_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flexspi0_region0_rule`]
659module"]
660#[doc(alias = "FLEXSPI0_REGION0_RULE")]
661pub type Flexspi0Region0Rule = crate::Reg<flexspi0_region0_rule::Flexspi0Region0RuleSpec>;
662#[doc = "FLEXSPI0 Region 0 Rule(n) Register"]
663pub mod flexspi0_region0_rule;
664#[doc = "FLEXSPI0_REGION1_RULE0 (rw) register accessor: FLEXSPI0 Region 1 Rule 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flexspi0_region1_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flexspi0_region1_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flexspi0_region1_rule0`]
665module"]
666#[doc(alias = "FLEXSPI0_REGION1_RULE0")]
667pub type Flexspi0Region1Rule0 = crate::Reg<flexspi0_region1_rule0::Flexspi0Region1Rule0Spec>;
668#[doc = "FLEXSPI0 Region 1 Rule 0 Register"]
669pub mod flexspi0_region1_rule0;
670#[doc = "FLEXSPI0_REGION2_RULE0 (rw) register accessor: FLEXSPI0 Region 2 Rule 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flexspi0_region2_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flexspi0_region2_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flexspi0_region2_rule0`]
671module"]
672#[doc(alias = "FLEXSPI0_REGION2_RULE0")]
673pub type Flexspi0Region2Rule0 = crate::Reg<flexspi0_region2_rule0::Flexspi0Region2Rule0Spec>;
674#[doc = "FLEXSPI0 Region 2 Rule 0 Register"]
675pub mod flexspi0_region2_rule0;
676#[doc = "FLEXSPI0_REGION3_RULE0 (rw) register accessor: FLEXSPI0 Region 3 Rule 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flexspi0_region3_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flexspi0_region3_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flexspi0_region3_rule0`]
677module"]
678#[doc(alias = "FLEXSPI0_REGION3_RULE0")]
679pub type Flexspi0Region3Rule0 = crate::Reg<flexspi0_region3_rule0::Flexspi0Region3Rule0Spec>;
680#[doc = "FLEXSPI0 Region 3 Rule 0 Register"]
681pub mod flexspi0_region3_rule0;
682#[doc = "FLEXSPI0_REGION4_RULE0 (rw) register accessor: FLEXSPI0 Region 4 Rule 0 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`flexspi0_region4_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flexspi0_region4_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flexspi0_region4_rule0`]
683module"]
684#[doc(alias = "FLEXSPI0_REGION4_RULE0")]
685pub type Flexspi0Region4Rule0 = crate::Reg<flexspi0_region4_rule0::Flexspi0Region4Rule0Spec>;
686#[doc = "FLEXSPI0 Region 4 Rule 0 Register"]
687pub mod flexspi0_region4_rule0;
688#[doc = "RAM00_RULE (rw) register accessor: SRAM Partition 00 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram00_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram00_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram00_rule`]
689module"]
690#[doc(alias = "RAM00_RULE")]
691pub type Ram00Rule = crate::Reg<ram00_rule::Ram00RuleSpec>;
692#[doc = "SRAM Partition 00 Rule(n) Register"]
693pub mod ram00_rule;
694#[doc = "RAM01_RULE (rw) register accessor: SRAM Partition 01 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram01_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram01_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram01_rule`]
695module"]
696#[doc(alias = "RAM01_RULE")]
697pub type Ram01Rule = crate::Reg<ram01_rule::Ram01RuleSpec>;
698#[doc = "SRAM Partition 01 Rule(n) Register"]
699pub mod ram01_rule;
700#[doc = "RAM02_RULE (rw) register accessor: SRAM Partition 02 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram02_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram02_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram02_rule`]
701module"]
702#[doc(alias = "RAM02_RULE")]
703pub type Ram02Rule = crate::Reg<ram02_rule::Ram02RuleSpec>;
704#[doc = "SRAM Partition 02 Rule(n) Register"]
705pub mod ram02_rule;
706#[doc = "RAM03_RULE (rw) register accessor: SRAM Partition 03 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram03_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram03_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram03_rule`]
707module"]
708#[doc(alias = "RAM03_RULE")]
709pub type Ram03Rule = crate::Reg<ram03_rule::Ram03RuleSpec>;
710#[doc = "SRAM Partition 03 Rule(n) Register"]
711pub mod ram03_rule;
712#[doc = "RAM04_RULE (rw) register accessor: SRAM Partition 04 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram04_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram04_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram04_rule`]
713module"]
714#[doc(alias = "RAM04_RULE")]
715pub type Ram04Rule = crate::Reg<ram04_rule::Ram04RuleSpec>;
716#[doc = "SRAM Partition 04 Rule(n) Register"]
717pub mod ram04_rule;
718#[doc = "RAM05_RULE (rw) register accessor: SRAM Partition 05 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram05_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram05_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram05_rule`]
719module"]
720#[doc(alias = "RAM05_RULE")]
721pub type Ram05Rule = crate::Reg<ram05_rule::Ram05RuleSpec>;
722#[doc = "SRAM Partition 05 Rule(n) Register"]
723pub mod ram05_rule;
724#[doc = "RAM06_RULE (rw) register accessor: SRAM Partition 06 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram06_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram06_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram06_rule`]
725module"]
726#[doc(alias = "RAM06_RULE")]
727pub type Ram06Rule = crate::Reg<ram06_rule::Ram06RuleSpec>;
728#[doc = "SRAM Partition 06 Rule(n) Register"]
729pub mod ram06_rule;
730#[doc = "RAM07_RULE (rw) register accessor: SRAM Partition 07 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram07_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram07_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram07_rule`]
731module"]
732#[doc(alias = "RAM07_RULE")]
733pub type Ram07Rule = crate::Reg<ram07_rule::Ram07RuleSpec>;
734#[doc = "SRAM Partition 07 Rule(n) Register"]
735pub mod ram07_rule;
736#[doc = "RAM08_RULE (rw) register accessor: SRAM Partition 08 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram08_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram08_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram08_rule`]
737module"]
738#[doc(alias = "RAM08_RULE")]
739pub type Ram08Rule = crate::Reg<ram08_rule::Ram08RuleSpec>;
740#[doc = "SRAM Partition 08 Rule(n) Register"]
741pub mod ram08_rule;
742#[doc = "RAM09_RULE (rw) register accessor: SRAM Partition 09 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram09_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram09_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram09_rule`]
743module"]
744#[doc(alias = "RAM09_RULE")]
745pub type Ram09Rule = crate::Reg<ram09_rule::Ram09RuleSpec>;
746#[doc = "SRAM Partition 09 Rule(n) Register"]
747pub mod ram09_rule;
748#[doc = "RAM10_RULE (rw) register accessor: SRAM Partition 10 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram10_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram10_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram10_rule`]
749module"]
750#[doc(alias = "RAM10_RULE")]
751pub type Ram10Rule = crate::Reg<ram10_rule::Ram10RuleSpec>;
752#[doc = "SRAM Partition 10 Rule(n) Register"]
753pub mod ram10_rule;
754#[doc = "RAM11_RULE (rw) register accessor: SRAM Partition 11 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram11_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram11_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram11_rule`]
755module"]
756#[doc(alias = "RAM11_RULE")]
757pub type Ram11Rule = crate::Reg<ram11_rule::Ram11RuleSpec>;
758#[doc = "SRAM Partition 11 Rule(n) Register"]
759pub mod ram11_rule;
760#[doc = "RAM12_RULE (rw) register accessor: SRAM Partition 12 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram12_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram12_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram12_rule`]
761module"]
762#[doc(alias = "RAM12_RULE")]
763pub type Ram12Rule = crate::Reg<ram12_rule::Ram12RuleSpec>;
764#[doc = "SRAM Partition 12 Rule(n) Register"]
765pub mod ram12_rule;
766#[doc = "RAM13_RULE (rw) register accessor: SRAM Partition 13 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram13_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram13_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram13_rule`]
767module"]
768#[doc(alias = "RAM13_RULE")]
769pub type Ram13Rule = crate::Reg<ram13_rule::Ram13RuleSpec>;
770#[doc = "SRAM Partition 13 Rule(n) Register"]
771pub mod ram13_rule;
772#[doc = "RAM14_RULE (rw) register accessor: SRAM Partition 14 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram14_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram14_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram14_rule`]
773module"]
774#[doc(alias = "RAM14_RULE")]
775pub type Ram14Rule = crate::Reg<ram14_rule::Ram14RuleSpec>;
776#[doc = "SRAM Partition 14 Rule(n) Register"]
777pub mod ram14_rule;
778#[doc = "RAM15_RULE (rw) register accessor: SRAM Partition 15 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram15_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram15_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram15_rule`]
779module"]
780#[doc(alias = "RAM15_RULE")]
781pub type Ram15Rule = crate::Reg<ram15_rule::Ram15RuleSpec>;
782#[doc = "SRAM Partition 15 Rule(n) Register"]
783pub mod ram15_rule;
784#[doc = "RAM16_RULE (rw) register accessor: SRAM Partition 16 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram16_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram16_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram16_rule`]
785module"]
786#[doc(alias = "RAM16_RULE")]
787pub type Ram16Rule = crate::Reg<ram16_rule::Ram16RuleSpec>;
788#[doc = "SRAM Partition 16 Rule(n) Register"]
789pub mod ram16_rule;
790#[doc = "RAM17_RULE (rw) register accessor: SRAM Partition 17 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram17_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram17_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram17_rule`]
791module"]
792#[doc(alias = "RAM17_RULE")]
793pub type Ram17Rule = crate::Reg<ram17_rule::Ram17RuleSpec>;
794#[doc = "SRAM Partition 17 Rule(n) Register"]
795pub mod ram17_rule;
796#[doc = "RAM18_RULE (rw) register accessor: SRAM Partition 18 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram18_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram18_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram18_rule`]
797module"]
798#[doc(alias = "RAM18_RULE")]
799pub type Ram18Rule = crate::Reg<ram18_rule::Ram18RuleSpec>;
800#[doc = "SRAM Partition 18 Rule(n) Register"]
801pub mod ram18_rule;
802#[doc = "RAM19_RULE (rw) register accessor: SRAM Partition 19 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram19_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram19_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram19_rule`]
803module"]
804#[doc(alias = "RAM19_RULE")]
805pub type Ram19Rule = crate::Reg<ram19_rule::Ram19RuleSpec>;
806#[doc = "SRAM Partition 19 Rule(n) Register"]
807pub mod ram19_rule;
808#[doc = "RAM20_RULE (rw) register accessor: SRAM Partition 20 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram20_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram20_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram20_rule`]
809module"]
810#[doc(alias = "RAM20_RULE")]
811pub type Ram20Rule = crate::Reg<ram20_rule::Ram20RuleSpec>;
812#[doc = "SRAM Partition 20 Rule(n) Register"]
813pub mod ram20_rule;
814#[doc = "RAM21_RULE (rw) register accessor: SRAM Partition 21 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram21_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram21_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram21_rule`]
815module"]
816#[doc(alias = "RAM21_RULE")]
817pub type Ram21Rule = crate::Reg<ram21_rule::Ram21RuleSpec>;
818#[doc = "SRAM Partition 21 Rule(n) Register"]
819pub mod ram21_rule;
820#[doc = "RAM22_RULE (rw) register accessor: SRAM Partition 22 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram22_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram22_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram22_rule`]
821module"]
822#[doc(alias = "RAM22_RULE")]
823pub type Ram22Rule = crate::Reg<ram22_rule::Ram22RuleSpec>;
824#[doc = "SRAM Partition 22 Rule(n) Register"]
825pub mod ram22_rule;
826#[doc = "RAM23_RULE (rw) register accessor: SRAM Partition 23 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram23_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram23_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram23_rule`]
827module"]
828#[doc(alias = "RAM23_RULE")]
829pub type Ram23Rule = crate::Reg<ram23_rule::Ram23RuleSpec>;
830#[doc = "SRAM Partition 23 Rule(n) Register"]
831pub mod ram23_rule;
832#[doc = "RAM24_RULE (rw) register accessor: SRAM Partition 24 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram24_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram24_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram24_rule`]
833module"]
834#[doc(alias = "RAM24_RULE")]
835pub type Ram24Rule = crate::Reg<ram24_rule::Ram24RuleSpec>;
836#[doc = "SRAM Partition 24 Rule(n) Register"]
837pub mod ram24_rule;
838#[doc = "RAM25_RULE (rw) register accessor: SRAM Partition 25 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram25_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram25_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram25_rule`]
839module"]
840#[doc(alias = "RAM25_RULE")]
841pub type Ram25Rule = crate::Reg<ram25_rule::Ram25RuleSpec>;
842#[doc = "SRAM Partition 25 Rule(n) Register"]
843pub mod ram25_rule;
844#[doc = "RAM26_RULE (rw) register accessor: SRAM Partition 26 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram26_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram26_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram26_rule`]
845module"]
846#[doc(alias = "RAM26_RULE")]
847pub type Ram26Rule = crate::Reg<ram26_rule::Ram26RuleSpec>;
848#[doc = "SRAM Partition 26 Rule(n) Register"]
849pub mod ram26_rule;
850#[doc = "RAM27_RULE (rw) register accessor: SRAM Partition 27 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram27_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram27_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram27_rule`]
851module"]
852#[doc(alias = "RAM27_RULE")]
853pub type Ram27Rule = crate::Reg<ram27_rule::Ram27RuleSpec>;
854#[doc = "SRAM Partition 27 Rule(n) Register"]
855pub mod ram27_rule;
856#[doc = "RAM28_RULE (rw) register accessor: SRAM Partition 28 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram28_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram28_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram28_rule`]
857module"]
858#[doc(alias = "RAM28_RULE")]
859pub type Ram28Rule = crate::Reg<ram28_rule::Ram28RuleSpec>;
860#[doc = "SRAM Partition 28 Rule(n) Register"]
861pub mod ram28_rule;
862#[doc = "RAM29_RULE (rw) register accessor: SRAM Partition 29 Rule(n) Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ram29_rule::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ram29_rule::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ram29_rule`]
863module"]
864#[doc(alias = "RAM29_RULE")]
865pub type Ram29Rule = crate::Reg<ram29_rule::Ram29RuleSpec>;
866#[doc = "SRAM Partition 29 Rule(n) Register"]
867pub mod ram29_rule;
868#[doc = "PIF_HIFI4_X_MEM_RULE0 (rw) register accessor: Security access rules for HiFi 4 memory sectors (0x24000000--0x240FFFFF). Each sector is 32 Kbytes, there're 4 sectors in total.\n\nYou can [`read`](crate::Reg::read) this register and get [`pif_hifi4_x_mem_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pif_hifi4_x_mem_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pif_hifi4_x_mem_rule0`]
869module"]
870#[doc(alias = "PIF_HIFI4_X_MEM_RULE0")]
871pub type PifHifi4XMemRule0 = crate::Reg<pif_hifi4_x_mem_rule0::PifHifi4XMemRule0Spec>;
872#[doc = "Security access rules for HiFi 4 memory sectors (0x24000000--0x240FFFFF). Each sector is 32 Kbytes, there're 4 sectors in total."]
873pub mod pif_hifi4_x_mem_rule0;
874#[doc = "APB_GRP0_MEM_RULE0 (rw) register accessor: Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total.\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_grp0_mem_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_grp0_mem_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb_grp0_mem_rule0`]
875module"]
876#[doc(alias = "APB_GRP0_MEM_RULE0")]
877pub type ApbGrp0MemRule0 = crate::Reg<apb_grp0_mem_rule0::ApbGrp0MemRule0Spec>;
878#[doc = "Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total."]
879pub mod apb_grp0_mem_rule0;
880#[doc = "APB_GRP0_MEM_RULE1 (rw) register accessor: Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total.\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_grp0_mem_rule1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_grp0_mem_rule1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb_grp0_mem_rule1`]
881module"]
882#[doc(alias = "APB_GRP0_MEM_RULE1")]
883pub type ApbGrp0MemRule1 = crate::Reg<apb_grp0_mem_rule1::ApbGrp0MemRule1Spec>;
884#[doc = "Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total."]
885pub mod apb_grp0_mem_rule1;
886#[doc = "APB_GRP1_MEM_RULE0 (rw) register accessor: Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total.\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_grp1_mem_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_grp1_mem_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb_grp1_mem_rule0`]
887module"]
888#[doc(alias = "APB_GRP1_MEM_RULE0")]
889pub type ApbGrp1MemRule0 = crate::Reg<apb_grp1_mem_rule0::ApbGrp1MemRule0Spec>;
890#[doc = "Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total."]
891pub mod apb_grp1_mem_rule0;
892#[doc = "APB_GRP1_MEM_RULE1 (rw) register accessor: Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total.\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_grp1_mem_rule1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_grp1_mem_rule1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb_grp1_mem_rule1`]
893module"]
894#[doc(alias = "APB_GRP1_MEM_RULE1")]
895pub type ApbGrp1MemRule1 = crate::Reg<apb_grp1_mem_rule1::ApbGrp1MemRule1Spec>;
896#[doc = "Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total."]
897pub mod apb_grp1_mem_rule1;
898#[doc = "APB_GRP1_MEM_RULE2 (rw) register accessor: Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total.\n\nYou can [`read`](crate::Reg::read) this register and get [`apb_grp1_mem_rule2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb_grp1_mem_rule2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb_grp1_mem_rule2`]
899module"]
900#[doc(alias = "APB_GRP1_MEM_RULE2")]
901pub type ApbGrp1MemRule2 = crate::Reg<apb_grp1_mem_rule2::ApbGrp1MemRule2Spec>;
902#[doc = "Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes, there're 16 sectors in total."]
903pub mod apb_grp1_mem_rule2;
904#[doc = "AHB_PERIPH0_SLAVE_RULE0 (rw) register accessor: Security access rules for AHB peripheral slaves area 0x40100000--0x4010FFFF\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_periph0_slave_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_periph0_slave_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_periph0_slave_rule0`]
905module"]
906#[doc(alias = "AHB_PERIPH0_SLAVE_RULE0")]
907pub type AhbPeriph0SlaveRule0 = crate::Reg<ahb_periph0_slave_rule0::AhbPeriph0SlaveRule0Spec>;
908#[doc = "Security access rules for AHB peripheral slaves area 0x40100000--0x4010FFFF"]
909pub mod ahb_periph0_slave_rule0;
910#[doc = "AIPS_BRIDGE0_MEM_RULE0 (rw) register accessor: 0x40110000--0x4011FFFF\n\nYou can [`read`](crate::Reg::read) this register and get [`aips_bridge0_mem_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aips_bridge0_mem_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aips_bridge0_mem_rule0`]
911module"]
912#[doc(alias = "AIPS_BRIDGE0_MEM_RULE0")]
913pub type AipsBridge0MemRule0 = crate::Reg<aips_bridge0_mem_rule0::AipsBridge0MemRule0Spec>;
914#[doc = "0x40110000--0x4011FFFF"]
915pub mod aips_bridge0_mem_rule0;
916#[doc = "AHB_PERIPH1_SLAVE_RULE0 (rw) register accessor: the memory map is 0x40120000--0x40127FFF\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_periph1_slave_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_periph1_slave_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_periph1_slave_rule0`]
917module"]
918#[doc(alias = "AHB_PERIPH1_SLAVE_RULE0")]
919pub type AhbPeriph1SlaveRule0 = crate::Reg<ahb_periph1_slave_rule0::AhbPeriph1SlaveRule0Spec>;
920#[doc = "the memory map is 0x40120000--0x40127FFF"]
921pub mod ahb_periph1_slave_rule0;
922#[doc = "AIPS_BRIDGE1_MEM_RULE0 (rw) register accessor: Security access rules for AIPS Bridge peripherals. Each AIPS bridge sector is 4 Kbytes, there're 16 sectors in total.\n\nYou can [`read`](crate::Reg::read) this register and get [`aips_bridge1_mem_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aips_bridge1_mem_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aips_bridge1_mem_rule0`]
923module"]
924#[doc(alias = "AIPS_BRIDGE1_MEM_RULE0")]
925pub type AipsBridge1MemRule0 = crate::Reg<aips_bridge1_mem_rule0::AipsBridge1MemRule0Spec>;
926#[doc = "Security access rules for AIPS Bridge peripherals. Each AIPS bridge sector is 4 Kbytes, there're 16 sectors in total."]
927pub mod aips_bridge1_mem_rule0;
928#[doc = "AIPS_BRIDGE1_MEM_RULE1 (rw) register accessor: Security access rules for AIPS Bridge peripherals. Each AIPS bridge sector is 4 Kbytes, there're 16 sectors in total.\n\nYou can [`read`](crate::Reg::read) this register and get [`aips_bridge1_mem_rule1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aips_bridge1_mem_rule1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aips_bridge1_mem_rule1`]
929module"]
930#[doc(alias = "AIPS_BRIDGE1_MEM_RULE1")]
931pub type AipsBridge1MemRule1 = crate::Reg<aips_bridge1_mem_rule1::AipsBridge1MemRule1Spec>;
932#[doc = "Security access rules for AIPS Bridge peripherals. Each AIPS bridge sector is 4 Kbytes, there're 16 sectors in total."]
933pub mod aips_bridge1_mem_rule1;
934#[doc = "AHB_PERIPH2_SLAVE_RULE0 (rw) register accessor: Security access rules for AHB peripheral slaves area 0x40140000--0x4014BFFF\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_periph2_slave_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_periph2_slave_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_periph2_slave_rule0`]
935module"]
936#[doc(alias = "AHB_PERIPH2_SLAVE_RULE0")]
937pub type AhbPeriph2SlaveRule0 = crate::Reg<ahb_periph2_slave_rule0::AhbPeriph2SlaveRule0Spec>;
938#[doc = "Security access rules for AHB peripheral slaves area 0x40140000--0x4014BFFF"]
939pub mod ahb_periph2_slave_rule0;
940#[doc = "SECURITY_CTRL_MEM_RULE0 (rw) register accessor: 0x40148000--0x4014BFFF\n\nYou can [`read`](crate::Reg::read) this register and get [`security_ctrl_mem_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`security_ctrl_mem_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@security_ctrl_mem_rule0`]
941module"]
942#[doc(alias = "SECURITY_CTRL_MEM_RULE0")]
943pub type SecurityCtrlMemRule0 = crate::Reg<security_ctrl_mem_rule0::SecurityCtrlMemRule0Spec>;
944#[doc = "0x40148000--0x4014BFFF"]
945pub mod security_ctrl_mem_rule0;
946#[doc = "AHB_PERIPH3_SLAVE_RULE0 (rw) register accessor: Security access rules for AHB peripheral slaves area 0x40150000--0x40158FFF\n\nYou can [`read`](crate::Reg::read) this register and get [`ahb_periph3_slave_rule0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb_periph3_slave_rule0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ahb_periph3_slave_rule0`]
947module"]
948#[doc(alias = "AHB_PERIPH3_SLAVE_RULE0")]
949pub type AhbPeriph3SlaveRule0 = crate::Reg<ahb_periph3_slave_rule0::AhbPeriph3SlaveRule0Spec>;
950#[doc = "Security access rules for AHB peripheral slaves area 0x40150000--0x40158FFF"]
951pub mod ahb_periph3_slave_rule0;
952#[doc = "SEC_VIO_ADDR (r) register accessor: most recent security violation address for AHB layer n\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_vio_addr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_vio_addr`]
953module"]
954#[doc(alias = "SEC_VIO_ADDR")]
955pub type SecVioAddr = crate::Reg<sec_vio_addr::SecVioAddrSpec>;
956#[doc = "most recent security violation address for AHB layer n"]
957pub mod sec_vio_addr;
958#[doc = "SEC_VIO_MISC_INFO (r) register accessor: most recent security violation miscellaneous information for AHB layer n\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_vio_misc_info::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_vio_misc_info`]
959module"]
960#[doc(alias = "SEC_VIO_MISC_INFO")]
961pub type SecVioMiscInfo = crate::Reg<sec_vio_misc_info::SecVioMiscInfoSpec>;
962#[doc = "most recent security violation miscellaneous information for AHB layer n"]
963pub mod sec_vio_misc_info;
964#[doc = "SEC_VIO_INFO_VALID (rw) register accessor: security violation address/information registers valid flags\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_vio_info_valid::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_vio_info_valid::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_vio_info_valid`]
965module"]
966#[doc(alias = "SEC_VIO_INFO_VALID")]
967pub type SecVioInfoValid = crate::Reg<sec_vio_info_valid::SecVioInfoValidSpec>;
968#[doc = "security violation address/information registers valid flags"]
969pub mod sec_vio_info_valid;
970#[doc = "SEC_GPIO_MASK0 (rw) register accessor: Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world.\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_gpio_mask0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_gpio_mask0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_gpio_mask0`]
971module"]
972#[doc(alias = "SEC_GPIO_MASK0")]
973pub type SecGpioMask0 = crate::Reg<sec_gpio_mask0::SecGpioMask0Spec>;
974#[doc = "Secure GPIO mask for port 0 pins. This register is used to block leakage of Secure interface (GPIOs, I2C, UART configured as secure peripherals) pin states to non-secure world."]
975pub mod sec_gpio_mask0;
976#[doc = "SEC_GPIO_MASK1 (rw) register accessor: Secure GPIO mask for port 1 pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_gpio_mask1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_gpio_mask1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_gpio_mask1`]
977module"]
978#[doc(alias = "SEC_GPIO_MASK1")]
979pub type SecGpioMask1 = crate::Reg<sec_gpio_mask1::SecGpioMask1Spec>;
980#[doc = "Secure GPIO mask for port 1 pins."]
981pub mod sec_gpio_mask1;
982#[doc = "SEC_GPIO_MASK2 (rw) register accessor: Secure GPIO mask for port 2 pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_gpio_mask2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_gpio_mask2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_gpio_mask2`]
983module"]
984#[doc(alias = "SEC_GPIO_MASK2")]
985pub type SecGpioMask2 = crate::Reg<sec_gpio_mask2::SecGpioMask2Spec>;
986#[doc = "Secure GPIO mask for port 2 pins."]
987pub mod sec_gpio_mask2;
988#[doc = "SEC_GPIO_MASK3 (rw) register accessor: Secure GPIO mask for port 3 pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_gpio_mask3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_gpio_mask3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_gpio_mask3`]
989module"]
990#[doc(alias = "SEC_GPIO_MASK3")]
991pub type SecGpioMask3 = crate::Reg<sec_gpio_mask3::SecGpioMask3Spec>;
992#[doc = "Secure GPIO mask for port 3 pins."]
993pub mod sec_gpio_mask3;
994#[doc = "SEC_GPIO_MASK4 (rw) register accessor: Secure GPIO mask for port 4 pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_gpio_mask4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_gpio_mask4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_gpio_mask4`]
995module"]
996#[doc(alias = "SEC_GPIO_MASK4")]
997pub type SecGpioMask4 = crate::Reg<sec_gpio_mask4::SecGpioMask4Spec>;
998#[doc = "Secure GPIO mask for port 4 pins."]
999pub mod sec_gpio_mask4;
1000#[doc = "SEC_GPIO_MASK5 (rw) register accessor: Secure GPIO mask for port 5 pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_gpio_mask5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_gpio_mask5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_gpio_mask5`]
1001module"]
1002#[doc(alias = "SEC_GPIO_MASK5")]
1003pub type SecGpioMask5 = crate::Reg<sec_gpio_mask5::SecGpioMask5Spec>;
1004#[doc = "Secure GPIO mask for port 5 pins."]
1005pub mod sec_gpio_mask5;
1006#[doc = "SEC_GPIO_MASK6 (rw) register accessor: Secure GPIO mask for port 6 pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_gpio_mask6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_gpio_mask6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_gpio_mask6`]
1007module"]
1008#[doc(alias = "SEC_GPIO_MASK6")]
1009pub type SecGpioMask6 = crate::Reg<sec_gpio_mask6::SecGpioMask6Spec>;
1010#[doc = "Secure GPIO mask for port 6 pins."]
1011pub mod sec_gpio_mask6;
1012#[doc = "SEC_GPIO_MASK7 (rw) register accessor: Secure GPIO mask for port 7 pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_gpio_mask7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_gpio_mask7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_gpio_mask7`]
1013module"]
1014#[doc(alias = "SEC_GPIO_MASK7")]
1015pub type SecGpioMask7 = crate::Reg<sec_gpio_mask7::SecGpioMask7Spec>;
1016#[doc = "Secure GPIO mask for port 7 pins."]
1017pub mod sec_gpio_mask7;
1018#[doc = "SEC_DSP_INT_MASK (rw) register accessor: secure general purpose register 8 used to mask interrupts to DSP for security purpose\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_dsp_int_mask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_dsp_int_mask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_dsp_int_mask`]
1019module"]
1020#[doc(alias = "SEC_DSP_INT_MASK")]
1021pub type SecDspIntMask = crate::Reg<sec_dsp_int_mask::SecDspIntMaskSpec>;
1022#[doc = "secure general purpose register 8 used to mask interrupts to DSP for security purpose"]
1023pub mod sec_dsp_int_mask;
1024#[doc = "SEC_MASK_LOCK (rw) register accessor: sec_gp_reg write-lock bits\n\nYou can [`read`](crate::Reg::read) this register and get [`sec_mask_lock::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sec_mask_lock::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sec_mask_lock`]
1025module"]
1026#[doc(alias = "SEC_MASK_LOCK")]
1027pub type SecMaskLock = crate::Reg<sec_mask_lock::SecMaskLockSpec>;
1028#[doc = "sec_gp_reg write-lock bits"]
1029pub mod sec_mask_lock;
1030#[doc = "MASTER_SEC_LEVEL (rw) register accessor: master secure level register\n\nYou can [`read`](crate::Reg::read) this register and get [`master_sec_level::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`master_sec_level::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@master_sec_level`]
1031module"]
1032#[doc(alias = "MASTER_SEC_LEVEL")]
1033pub type MasterSecLevel = crate::Reg<master_sec_level::MasterSecLevelSpec>;
1034#[doc = "master secure level register"]
1035pub mod master_sec_level;
1036#[doc = "MASTER_SEC_LEVEL_ANTI_POL (rw) register accessor: master secure level anti-pole register\n\nYou can [`read`](crate::Reg::read) this register and get [`master_sec_level_anti_pol::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`master_sec_level_anti_pol::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@master_sec_level_anti_pol`]
1037module"]
1038#[doc(alias = "MASTER_SEC_LEVEL_ANTI_POL")]
1039pub type MasterSecLevelAntiPol = crate::Reg<master_sec_level_anti_pol::MasterSecLevelAntiPolSpec>;
1040#[doc = "master secure level anti-pole register"]
1041pub mod master_sec_level_anti_pol;
1042#[doc = "CM33_LOCK_REG (rw) register accessor: m33 lock control register\n\nYou can [`read`](crate::Reg::read) this register and get [`cm33_lock_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cm33_lock_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cm33_lock_reg`]
1043module"]
1044#[doc(alias = "CM33_LOCK_REG")]
1045pub type Cm33LockReg = crate::Reg<cm33_lock_reg::Cm33LockRegSpec>;
1046#[doc = "m33 lock control register"]
1047pub mod cm33_lock_reg;
1048#[doc = "MISC_CTRL_DP_REG (rw) register accessor: secure control duplicate register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc_ctrl_dp_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc_ctrl_dp_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@misc_ctrl_dp_reg`]
1049module"]
1050#[doc(alias = "MISC_CTRL_DP_REG")]
1051pub type MiscCtrlDpReg = crate::Reg<misc_ctrl_dp_reg::MiscCtrlDpRegSpec>;
1052#[doc = "secure control duplicate register"]
1053pub mod misc_ctrl_dp_reg;
1054#[doc = "MISC_CTRL_REG (rw) register accessor: secure control register\n\nYou can [`read`](crate::Reg::read) this register and get [`misc_ctrl_reg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`misc_ctrl_reg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@misc_ctrl_reg`]
1055module"]
1056#[doc(alias = "MISC_CTRL_REG")]
1057pub type MiscCtrlReg = crate::Reg<misc_ctrl_reg::MiscCtrlRegSpec>;
1058#[doc = "secure control register"]
1059pub mod misc_ctrl_reg;