1#[doc = "Register `CFG` reader"]
2pub type R = crate::R<CfgSpec>;
3#[doc = "Register `CFG` writer"]
4pub type W = crate::W<CfgSpec>;
5#[doc = "ADC trigger priority control\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Tprictrl {
9 #[doc = "0: If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."]
10 Tprictrl0 = 0,
11 #[doc = "1: If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated."]
12 Tprictrl1 = 1,
13}
14impl From<Tprictrl> for bool {
15 #[inline(always)]
16 fn from(variant: Tprictrl) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `TPRICTRL` reader - ADC trigger priority control"]
21pub type TprictrlR = crate::BitReader<Tprictrl>;
22impl TprictrlR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> Tprictrl {
26 match self.bits {
27 false => Tprictrl::Tprictrl0,
28 true => Tprictrl::Tprictrl1,
29 }
30 }
31 #[doc = "If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."]
32 #[inline(always)]
33 pub fn is_tprictrl_0(&self) -> bool {
34 *self == Tprictrl::Tprictrl0
35 }
36 #[doc = "If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated."]
37 #[inline(always)]
38 pub fn is_tprictrl_1(&self) -> bool {
39 *self == Tprictrl::Tprictrl1
40 }
41}
42#[doc = "Field `TPRICTRL` writer - ADC trigger priority control"]
43pub type TprictrlW<'a, REG> = crate::BitWriter<'a, REG, Tprictrl>;
44impl<'a, REG> TprictrlW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."]
49 #[inline(always)]
50 pub fn tprictrl_0(self) -> &'a mut crate::W<REG> {
51 self.variant(Tprictrl::Tprictrl0)
52 }
53 #[doc = "If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations and compare function if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated."]
54 #[inline(always)]
55 pub fn tprictrl_1(self) -> &'a mut crate::W<REG> {
56 self.variant(Tprictrl::Tprictrl1)
57 }
58}
59#[doc = "Power Configuration Select\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62#[repr(u8)]
63pub enum Pwrsel {
64 #[doc = "0: Lowest power setting."]
65 Pwrsel0 = 0,
66 #[doc = "1: Next lowest power setting."]
67 Pwrsel1 = 1,
68 #[doc = "2: ...."]
69 Pwrsel2 = 2,
70 #[doc = "3: Highest power setting."]
71 Pwrsel3 = 3,
72}
73impl From<Pwrsel> for u8 {
74 #[inline(always)]
75 fn from(variant: Pwrsel) -> Self {
76 variant as _
77 }
78}
79impl crate::FieldSpec for Pwrsel {
80 type Ux = u8;
81}
82impl crate::IsEnum for Pwrsel {}
83#[doc = "Field `PWRSEL` reader - Power Configuration Select"]
84pub type PwrselR = crate::FieldReader<Pwrsel>;
85impl PwrselR {
86 #[doc = "Get enumerated values variant"]
87 #[inline(always)]
88 pub const fn variant(&self) -> Pwrsel {
89 match self.bits {
90 0 => Pwrsel::Pwrsel0,
91 1 => Pwrsel::Pwrsel1,
92 2 => Pwrsel::Pwrsel2,
93 3 => Pwrsel::Pwrsel3,
94 _ => unreachable!(),
95 }
96 }
97 #[doc = "Lowest power setting."]
98 #[inline(always)]
99 pub fn is_pwrsel_0(&self) -> bool {
100 *self == Pwrsel::Pwrsel0
101 }
102 #[doc = "Next lowest power setting."]
103 #[inline(always)]
104 pub fn is_pwrsel_1(&self) -> bool {
105 *self == Pwrsel::Pwrsel1
106 }
107 #[doc = "...."]
108 #[inline(always)]
109 pub fn is_pwrsel_2(&self) -> bool {
110 *self == Pwrsel::Pwrsel2
111 }
112 #[doc = "Highest power setting."]
113 #[inline(always)]
114 pub fn is_pwrsel_3(&self) -> bool {
115 *self == Pwrsel::Pwrsel3
116 }
117}
118#[doc = "Field `PWRSEL` writer - Power Configuration Select"]
119pub type PwrselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pwrsel, crate::Safe>;
120impl<'a, REG> PwrselW<'a, REG>
121where
122 REG: crate::Writable + crate::RegisterSpec,
123 REG::Ux: From<u8>,
124{
125 #[doc = "Lowest power setting."]
126 #[inline(always)]
127 pub fn pwrsel_0(self) -> &'a mut crate::W<REG> {
128 self.variant(Pwrsel::Pwrsel0)
129 }
130 #[doc = "Next lowest power setting."]
131 #[inline(always)]
132 pub fn pwrsel_1(self) -> &'a mut crate::W<REG> {
133 self.variant(Pwrsel::Pwrsel1)
134 }
135 #[doc = "...."]
136 #[inline(always)]
137 pub fn pwrsel_2(self) -> &'a mut crate::W<REG> {
138 self.variant(Pwrsel::Pwrsel2)
139 }
140 #[doc = "Highest power setting."]
141 #[inline(always)]
142 pub fn pwrsel_3(self) -> &'a mut crate::W<REG> {
143 self.variant(Pwrsel::Pwrsel3)
144 }
145}
146#[doc = "Voltage Reference Selection\n\nValue on reset: 0"]
147#[cfg_attr(feature = "defmt", derive(defmt::Format))]
148#[derive(Clone, Copy, Debug, PartialEq, Eq)]
149#[repr(u8)]
150pub enum Refsel {
151 #[doc = "0: (Default) Option 1 setting."]
152 Refsel0 = 0,
153 #[doc = "1: Option 2 setting."]
154 Refsel1 = 1,
155 #[doc = "2: Option 3 setting."]
156 Refsel2 = 2,
157}
158impl From<Refsel> for u8 {
159 #[inline(always)]
160 fn from(variant: Refsel) -> Self {
161 variant as _
162 }
163}
164impl crate::FieldSpec for Refsel {
165 type Ux = u8;
166}
167impl crate::IsEnum for Refsel {}
168#[doc = "Field `REFSEL` reader - Voltage Reference Selection"]
169pub type RefselR = crate::FieldReader<Refsel>;
170impl RefselR {
171 #[doc = "Get enumerated values variant"]
172 #[inline(always)]
173 pub const fn variant(&self) -> Option<Refsel> {
174 match self.bits {
175 0 => Some(Refsel::Refsel0),
176 1 => Some(Refsel::Refsel1),
177 2 => Some(Refsel::Refsel2),
178 _ => None,
179 }
180 }
181 #[doc = "(Default) Option 1 setting."]
182 #[inline(always)]
183 pub fn is_refsel_0(&self) -> bool {
184 *self == Refsel::Refsel0
185 }
186 #[doc = "Option 2 setting."]
187 #[inline(always)]
188 pub fn is_refsel_1(&self) -> bool {
189 *self == Refsel::Refsel1
190 }
191 #[doc = "Option 3 setting."]
192 #[inline(always)]
193 pub fn is_refsel_2(&self) -> bool {
194 *self == Refsel::Refsel2
195 }
196}
197#[doc = "Field `REFSEL` writer - Voltage Reference Selection"]
198pub type RefselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Refsel>;
199impl<'a, REG> RefselW<'a, REG>
200where
201 REG: crate::Writable + crate::RegisterSpec,
202 REG::Ux: From<u8>,
203{
204 #[doc = "(Default) Option 1 setting."]
205 #[inline(always)]
206 pub fn refsel_0(self) -> &'a mut crate::W<REG> {
207 self.variant(Refsel::Refsel0)
208 }
209 #[doc = "Option 2 setting."]
210 #[inline(always)]
211 pub fn refsel_1(self) -> &'a mut crate::W<REG> {
212 self.variant(Refsel::Refsel1)
213 }
214 #[doc = "Option 3 setting."]
215 #[inline(always)]
216 pub fn refsel_2(self) -> &'a mut crate::W<REG> {
217 self.variant(Refsel::Refsel2)
218 }
219}
220#[doc = "Field `PUDLY` reader - Power Up Delay"]
221pub type PudlyR = crate::FieldReader;
222#[doc = "Field `PUDLY` writer - Power Up Delay"]
223pub type PudlyW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
224#[doc = "ADC Analog Pre-Enable\n\nValue on reset: 0"]
225#[cfg_attr(feature = "defmt", derive(defmt::Format))]
226#[derive(Clone, Copy, Debug, PartialEq, Eq)]
227pub enum Pwren {
228 #[doc = "0: ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays."]
229 Pwren0 = 0,
230 #[doc = "1: ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed."]
231 Pwren1 = 1,
232}
233impl From<Pwren> for bool {
234 #[inline(always)]
235 fn from(variant: Pwren) -> Self {
236 variant as u8 != 0
237 }
238}
239#[doc = "Field `PWREN` reader - ADC Analog Pre-Enable"]
240pub type PwrenR = crate::BitReader<Pwren>;
241impl PwrenR {
242 #[doc = "Get enumerated values variant"]
243 #[inline(always)]
244 pub const fn variant(&self) -> Pwren {
245 match self.bits {
246 false => Pwren::Pwren0,
247 true => Pwren::Pwren1,
248 }
249 }
250 #[doc = "ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays."]
251 #[inline(always)]
252 pub fn is_pwren_0(&self) -> bool {
253 *self == Pwren::Pwren0
254 }
255 #[doc = "ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed."]
256 #[inline(always)]
257 pub fn is_pwren_1(&self) -> bool {
258 *self == Pwren::Pwren1
259 }
260}
261#[doc = "Field `PWREN` writer - ADC Analog Pre-Enable"]
262pub type PwrenW<'a, REG> = crate::BitWriter<'a, REG, Pwren>;
263impl<'a, REG> PwrenW<'a, REG>
264where
265 REG: crate::Writable + crate::RegisterSpec,
266{
267 #[doc = "ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays."]
268 #[inline(always)]
269 pub fn pwren_0(self) -> &'a mut crate::W<REG> {
270 self.variant(Pwren::Pwren0)
271 }
272 #[doc = "ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed."]
273 #[inline(always)]
274 pub fn pwren_1(self) -> &'a mut crate::W<REG> {
275 self.variant(Pwren::Pwren1)
276 }
277}
278impl R {
279 #[doc = "Bit 0 - ADC trigger priority control"]
280 #[inline(always)]
281 pub fn tprictrl(&self) -> TprictrlR {
282 TprictrlR::new((self.bits & 1) != 0)
283 }
284 #[doc = "Bits 4:5 - Power Configuration Select"]
285 #[inline(always)]
286 pub fn pwrsel(&self) -> PwrselR {
287 PwrselR::new(((self.bits >> 4) & 3) as u8)
288 }
289 #[doc = "Bits 6:7 - Voltage Reference Selection"]
290 #[inline(always)]
291 pub fn refsel(&self) -> RefselR {
292 RefselR::new(((self.bits >> 6) & 3) as u8)
293 }
294 #[doc = "Bits 16:23 - Power Up Delay"]
295 #[inline(always)]
296 pub fn pudly(&self) -> PudlyR {
297 PudlyR::new(((self.bits >> 16) & 0xff) as u8)
298 }
299 #[doc = "Bit 28 - ADC Analog Pre-Enable"]
300 #[inline(always)]
301 pub fn pwren(&self) -> PwrenR {
302 PwrenR::new(((self.bits >> 28) & 1) != 0)
303 }
304}
305#[cfg(feature = "debug")]
306impl core::fmt::Debug for R {
307 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
308 f.debug_struct("CFG")
309 .field("tprictrl", &self.tprictrl())
310 .field("pwrsel", &self.pwrsel())
311 .field("refsel", &self.refsel())
312 .field("pudly", &self.pudly())
313 .field("pwren", &self.pwren())
314 .finish()
315 }
316}
317impl W {
318 #[doc = "Bit 0 - ADC trigger priority control"]
319 #[inline(always)]
320 pub fn tprictrl(&mut self) -> TprictrlW<CfgSpec> {
321 TprictrlW::new(self, 0)
322 }
323 #[doc = "Bits 4:5 - Power Configuration Select"]
324 #[inline(always)]
325 pub fn pwrsel(&mut self) -> PwrselW<CfgSpec> {
326 PwrselW::new(self, 4)
327 }
328 #[doc = "Bits 6:7 - Voltage Reference Selection"]
329 #[inline(always)]
330 pub fn refsel(&mut self) -> RefselW<CfgSpec> {
331 RefselW::new(self, 6)
332 }
333 #[doc = "Bits 16:23 - Power Up Delay"]
334 #[inline(always)]
335 pub fn pudly(&mut self) -> PudlyW<CfgSpec> {
336 PudlyW::new(self, 16)
337 }
338 #[doc = "Bit 28 - ADC Analog Pre-Enable"]
339 #[inline(always)]
340 pub fn pwren(&mut self) -> PwrenW<CfgSpec> {
341 PwrenW::new(self, 28)
342 }
343}
344#[doc = "ADC Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
345pub struct CfgSpec;
346impl crate::RegisterSpec for CfgSpec {
347 type Ux = u32;
348}
349#[doc = "`read()` method returns [`cfg::R`](R) reader structure"]
350impl crate::Readable for CfgSpec {}
351#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"]
352impl crate::Writable for CfgSpec {
353 type Safety = crate::Unsafe;
354 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
355 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
356}
357#[doc = "`reset()` method sets CFG to value 0x0080_0000"]
358impl crate::Resettable for CfgSpec {
359 const RESET_VALUE: u32 = 0x0080_0000;
360}