1#[doc = "Register `MCTRL` reader"]
2pub type R = crate::R<MctrlSpec>;
3#[doc = "Register `MCTRL` writer"]
4pub type W = crate::W<MctrlSpec>;
5#[doc = "Request\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Request {
10 #[doc = "0: NONE: Returns to this when finished with any request. The MSTATUS register indicates the master's state. See also AutoIBI mode. NONE is only written as 0: when setting RDTERM to 1 (to stop a read in progress) or when setting IBI reponse field (IBIRESP) for MSG use"]
11 None = 0,
12 #[doc = "1: EMITSTARTADDR: Emit START with address and direction from a stopped state or in the middle of a Single Data Rate (SDR) message. If from a stopped state (IDLE), then emit start may be prevented by an event (like IBI, MR, HJ), in which case the appropriate interrupt is signaled; note that Emit START can be resubmitted."]
13 Emitstartaddr = 1,
14 #[doc = "2: EMITSTOP: Emit a STOP on bus. Must be in Single Data Rate (SDR) mode. If in Dynamic Address Assignment (DAA) mode, Emit stop will exit DAA mode."]
15 Emitstop = 2,
16 #[doc = "3: IBIACKNACK: Manual In-Band Interrupt (IBI) Acknowledge (ACK) or Not Acknowledge (NACK). When IBIRESP has indicated a hold on an In-Band Interrupt to allow a manual decision, this request completes it. Uses IBIRESP to provide the information."]
17 Ibiacknack = 3,
18 #[doc = "4: PROCESSDAA: If not in Dynamic Address Assignment (DAA) mode now, will issue START, 7E, ENTDAA, and then will emit 7E/R to process each slave. Will stop just before the new Dynamic Address (DA) is to be emitted. The next Process DAA request will use the Addr field as the new DA to assign. If NACKed on the 7E/R, then the interrupt will indicate this situation, and a STOP will be emitted."]
19 Processdaa = 4,
20 #[doc = "6: FORCEEXIT and IBHR: Emit an Exit Pattern from any state, but end Double Data Rate (DDR) (including MSGDDR), if in DDR mode now. Includes a STOP afterward. If TYPE != 0, then it will perform an IBHR (In-Band Hardware Reset). If TYPE=2, then it does a normal reset (DEFRST can prevent the reset). If TYPE=3, it does a forced reset (will always reset)."]
21 Forceexit = 6,
22 #[doc = "7: AUTOIBI: Hold in a stopped state, but auto-emit START,7E when the slave is holding down SDA to get an In-Band Interrupt (IBI). Actual In-Band Interrupt handling is defined by IBIRESP."]
23 Autoibi = 7,
24}
25impl From<Request> for u8 {
26 #[inline(always)]
27 fn from(variant: Request) -> Self {
28 variant as _
29 }
30}
31impl crate::FieldSpec for Request {
32 type Ux = u8;
33}
34impl crate::IsEnum for Request {}
35#[doc = "Field `REQUEST` reader - Request"]
36pub type RequestR = crate::FieldReader<Request>;
37impl RequestR {
38 #[doc = "Get enumerated values variant"]
39 #[inline(always)]
40 pub const fn variant(&self) -> Option<Request> {
41 match self.bits {
42 0 => Some(Request::None),
43 1 => Some(Request::Emitstartaddr),
44 2 => Some(Request::Emitstop),
45 3 => Some(Request::Ibiacknack),
46 4 => Some(Request::Processdaa),
47 6 => Some(Request::Forceexit),
48 7 => Some(Request::Autoibi),
49 _ => None,
50 }
51 }
52 #[doc = "NONE: Returns to this when finished with any request. The MSTATUS register indicates the master's state. See also AutoIBI mode. NONE is only written as 0: when setting RDTERM to 1 (to stop a read in progress) or when setting IBI reponse field (IBIRESP) for MSG use"]
53 #[inline(always)]
54 pub fn is_none(&self) -> bool {
55 *self == Request::None
56 }
57 #[doc = "EMITSTARTADDR: Emit START with address and direction from a stopped state or in the middle of a Single Data Rate (SDR) message. If from a stopped state (IDLE), then emit start may be prevented by an event (like IBI, MR, HJ), in which case the appropriate interrupt is signaled; note that Emit START can be resubmitted."]
58 #[inline(always)]
59 pub fn is_emitstartaddr(&self) -> bool {
60 *self == Request::Emitstartaddr
61 }
62 #[doc = "EMITSTOP: Emit a STOP on bus. Must be in Single Data Rate (SDR) mode. If in Dynamic Address Assignment (DAA) mode, Emit stop will exit DAA mode."]
63 #[inline(always)]
64 pub fn is_emitstop(&self) -> bool {
65 *self == Request::Emitstop
66 }
67 #[doc = "IBIACKNACK: Manual In-Band Interrupt (IBI) Acknowledge (ACK) or Not Acknowledge (NACK). When IBIRESP has indicated a hold on an In-Band Interrupt to allow a manual decision, this request completes it. Uses IBIRESP to provide the information."]
68 #[inline(always)]
69 pub fn is_ibiacknack(&self) -> bool {
70 *self == Request::Ibiacknack
71 }
72 #[doc = "PROCESSDAA: If not in Dynamic Address Assignment (DAA) mode now, will issue START, 7E, ENTDAA, and then will emit 7E/R to process each slave. Will stop just before the new Dynamic Address (DA) is to be emitted. The next Process DAA request will use the Addr field as the new DA to assign. If NACKed on the 7E/R, then the interrupt will indicate this situation, and a STOP will be emitted."]
73 #[inline(always)]
74 pub fn is_processdaa(&self) -> bool {
75 *self == Request::Processdaa
76 }
77 #[doc = "FORCEEXIT and IBHR: Emit an Exit Pattern from any state, but end Double Data Rate (DDR) (including MSGDDR), if in DDR mode now. Includes a STOP afterward. If TYPE != 0, then it will perform an IBHR (In-Band Hardware Reset). If TYPE=2, then it does a normal reset (DEFRST can prevent the reset). If TYPE=3, it does a forced reset (will always reset)."]
78 #[inline(always)]
79 pub fn is_forceexit(&self) -> bool {
80 *self == Request::Forceexit
81 }
82 #[doc = "AUTOIBI: Hold in a stopped state, but auto-emit START,7E when the slave is holding down SDA to get an In-Band Interrupt (IBI). Actual In-Band Interrupt handling is defined by IBIRESP."]
83 #[inline(always)]
84 pub fn is_autoibi(&self) -> bool {
85 *self == Request::Autoibi
86 }
87}
88#[doc = "Field `REQUEST` writer - Request"]
89pub type RequestW<'a, REG> = crate::FieldWriter<'a, REG, 3, Request>;
90impl<'a, REG> RequestW<'a, REG>
91where
92 REG: crate::Writable + crate::RegisterSpec,
93 REG::Ux: From<u8>,
94{
95 #[doc = "NONE: Returns to this when finished with any request. The MSTATUS register indicates the master's state. See also AutoIBI mode. NONE is only written as 0: when setting RDTERM to 1 (to stop a read in progress) or when setting IBI reponse field (IBIRESP) for MSG use"]
96 #[inline(always)]
97 pub fn none(self) -> &'a mut crate::W<REG> {
98 self.variant(Request::None)
99 }
100 #[doc = "EMITSTARTADDR: Emit START with address and direction from a stopped state or in the middle of a Single Data Rate (SDR) message. If from a stopped state (IDLE), then emit start may be prevented by an event (like IBI, MR, HJ), in which case the appropriate interrupt is signaled; note that Emit START can be resubmitted."]
101 #[inline(always)]
102 pub fn emitstartaddr(self) -> &'a mut crate::W<REG> {
103 self.variant(Request::Emitstartaddr)
104 }
105 #[doc = "EMITSTOP: Emit a STOP on bus. Must be in Single Data Rate (SDR) mode. If in Dynamic Address Assignment (DAA) mode, Emit stop will exit DAA mode."]
106 #[inline(always)]
107 pub fn emitstop(self) -> &'a mut crate::W<REG> {
108 self.variant(Request::Emitstop)
109 }
110 #[doc = "IBIACKNACK: Manual In-Band Interrupt (IBI) Acknowledge (ACK) or Not Acknowledge (NACK). When IBIRESP has indicated a hold on an In-Band Interrupt to allow a manual decision, this request completes it. Uses IBIRESP to provide the information."]
111 #[inline(always)]
112 pub fn ibiacknack(self) -> &'a mut crate::W<REG> {
113 self.variant(Request::Ibiacknack)
114 }
115 #[doc = "PROCESSDAA: If not in Dynamic Address Assignment (DAA) mode now, will issue START, 7E, ENTDAA, and then will emit 7E/R to process each slave. Will stop just before the new Dynamic Address (DA) is to be emitted. The next Process DAA request will use the Addr field as the new DA to assign. If NACKed on the 7E/R, then the interrupt will indicate this situation, and a STOP will be emitted."]
116 #[inline(always)]
117 pub fn processdaa(self) -> &'a mut crate::W<REG> {
118 self.variant(Request::Processdaa)
119 }
120 #[doc = "FORCEEXIT and IBHR: Emit an Exit Pattern from any state, but end Double Data Rate (DDR) (including MSGDDR), if in DDR mode now. Includes a STOP afterward. If TYPE != 0, then it will perform an IBHR (In-Band Hardware Reset). If TYPE=2, then it does a normal reset (DEFRST can prevent the reset). If TYPE=3, it does a forced reset (will always reset)."]
121 #[inline(always)]
122 pub fn forceexit(self) -> &'a mut crate::W<REG> {
123 self.variant(Request::Forceexit)
124 }
125 #[doc = "AUTOIBI: Hold in a stopped state, but auto-emit START,7E when the slave is holding down SDA to get an In-Band Interrupt (IBI). Actual In-Band Interrupt handling is defined by IBIRESP."]
126 #[inline(always)]
127 pub fn autoibi(self) -> &'a mut crate::W<REG> {
128 self.variant(Request::Autoibi)
129 }
130}
131#[doc = "Bus type with START\n\nValue on reset: 0"]
132#[cfg_attr(feature = "defmt", derive(defmt::Format))]
133#[derive(Clone, Copy, Debug, PartialEq, Eq)]
134#[repr(u8)]
135pub enum Type {
136 #[doc = "0: I3C: Normally the SDR mode of I3C. For ForceExit, the Exit pattern."]
137 I3c = 0,
138 #[doc = "1: I2C: Normally the Standard I2C protocol."]
139 I2c = 1,
140 #[doc = "2: DDR: (Double Data Rate): Normally the HDR-DDR mode of I3C. Enter DDR mode (7E and then ENTHDR0), if the module is not already in DDR mode. The 1st byte written to the TX FIFO should be a command, and should already be in the FIFO. To end DDR mode, use ForceExit. For ForceExit, the normal IBHR (In-Band Hardware Reset)."]
141 Ddr = 2,
142 #[doc = "3: For ForcedExit, this is forced IBHR."]
143 Forcedibhr = 3,
144}
145impl From<Type> for u8 {
146 #[inline(always)]
147 fn from(variant: Type) -> Self {
148 variant as _
149 }
150}
151impl crate::FieldSpec for Type {
152 type Ux = u8;
153}
154impl crate::IsEnum for Type {}
155#[doc = "Field `TYPE` reader - Bus type with START"]
156pub type TypeR = crate::FieldReader<Type>;
157impl TypeR {
158 #[doc = "Get enumerated values variant"]
159 #[inline(always)]
160 pub const fn variant(&self) -> Type {
161 match self.bits {
162 0 => Type::I3c,
163 1 => Type::I2c,
164 2 => Type::Ddr,
165 3 => Type::Forcedibhr,
166 _ => unreachable!(),
167 }
168 }
169 #[doc = "I3C: Normally the SDR mode of I3C. For ForceExit, the Exit pattern."]
170 #[inline(always)]
171 pub fn is_i3c(&self) -> bool {
172 *self == Type::I3c
173 }
174 #[doc = "I2C: Normally the Standard I2C protocol."]
175 #[inline(always)]
176 pub fn is_i2c(&self) -> bool {
177 *self == Type::I2c
178 }
179 #[doc = "DDR: (Double Data Rate): Normally the HDR-DDR mode of I3C. Enter DDR mode (7E and then ENTHDR0), if the module is not already in DDR mode. The 1st byte written to the TX FIFO should be a command, and should already be in the FIFO. To end DDR mode, use ForceExit. For ForceExit, the normal IBHR (In-Band Hardware Reset)."]
180 #[inline(always)]
181 pub fn is_ddr(&self) -> bool {
182 *self == Type::Ddr
183 }
184 #[doc = "For ForcedExit, this is forced IBHR."]
185 #[inline(always)]
186 pub fn is_forcedibhr(&self) -> bool {
187 *self == Type::Forcedibhr
188 }
189}
190#[doc = "Field `TYPE` writer - Bus type with START"]
191pub type TypeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Type, crate::Safe>;
192impl<'a, REG> TypeW<'a, REG>
193where
194 REG: crate::Writable + crate::RegisterSpec,
195 REG::Ux: From<u8>,
196{
197 #[doc = "I3C: Normally the SDR mode of I3C. For ForceExit, the Exit pattern."]
198 #[inline(always)]
199 pub fn i3c(self) -> &'a mut crate::W<REG> {
200 self.variant(Type::I3c)
201 }
202 #[doc = "I2C: Normally the Standard I2C protocol."]
203 #[inline(always)]
204 pub fn i2c(self) -> &'a mut crate::W<REG> {
205 self.variant(Type::I2c)
206 }
207 #[doc = "DDR: (Double Data Rate): Normally the HDR-DDR mode of I3C. Enter DDR mode (7E and then ENTHDR0), if the module is not already in DDR mode. The 1st byte written to the TX FIFO should be a command, and should already be in the FIFO. To end DDR mode, use ForceExit. For ForceExit, the normal IBHR (In-Band Hardware Reset)."]
208 #[inline(always)]
209 pub fn ddr(self) -> &'a mut crate::W<REG> {
210 self.variant(Type::Ddr)
211 }
212 #[doc = "For ForcedExit, this is forced IBHR."]
213 #[inline(always)]
214 pub fn forcedibhr(self) -> &'a mut crate::W<REG> {
215 self.variant(Type::Forcedibhr)
216 }
217}
218#[doc = "In-Band Interrupt (IBI) response\n\nValue on reset: 0"]
219#[cfg_attr(feature = "defmt", derive(defmt::Format))]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221#[repr(u8)]
222pub enum Ibiresp {
223 #[doc = "0: ACK: Acknowledge. A mandatory byte (or not) is decided by the Master In-band Interrupt Registry and Rules Register (MIBIRULES). To limit the maximum number of IBI bytes, configure the Read Termination field (MCTRL.RDTERM)."]
224 Ack = 0,
225 #[doc = "1: NACK: Not acknowledge"]
226 Nack = 1,
227 #[doc = "2: ACK_WITH_MANDATORY: Acknowledge with mandatory byte (ignores the MIBIRULES register). Acknowledge with mandatory byte should not be used, unless only slaves with a mandatory byte can cause an In-Band Interrupt."]
228 AckWithMandatory = 2,
229 #[doc = "3: MANUAL: stop and wait for a decision using the IBIAckNack request"]
230 Manual = 3,
231}
232impl From<Ibiresp> for u8 {
233 #[inline(always)]
234 fn from(variant: Ibiresp) -> Self {
235 variant as _
236 }
237}
238impl crate::FieldSpec for Ibiresp {
239 type Ux = u8;
240}
241impl crate::IsEnum for Ibiresp {}
242#[doc = "Field `IBIRESP` reader - In-Band Interrupt (IBI) response"]
243pub type IbirespR = crate::FieldReader<Ibiresp>;
244impl IbirespR {
245 #[doc = "Get enumerated values variant"]
246 #[inline(always)]
247 pub const fn variant(&self) -> Ibiresp {
248 match self.bits {
249 0 => Ibiresp::Ack,
250 1 => Ibiresp::Nack,
251 2 => Ibiresp::AckWithMandatory,
252 3 => Ibiresp::Manual,
253 _ => unreachable!(),
254 }
255 }
256 #[doc = "ACK: Acknowledge. A mandatory byte (or not) is decided by the Master In-band Interrupt Registry and Rules Register (MIBIRULES). To limit the maximum number of IBI bytes, configure the Read Termination field (MCTRL.RDTERM)."]
257 #[inline(always)]
258 pub fn is_ack(&self) -> bool {
259 *self == Ibiresp::Ack
260 }
261 #[doc = "NACK: Not acknowledge"]
262 #[inline(always)]
263 pub fn is_nack(&self) -> bool {
264 *self == Ibiresp::Nack
265 }
266 #[doc = "ACK_WITH_MANDATORY: Acknowledge with mandatory byte (ignores the MIBIRULES register). Acknowledge with mandatory byte should not be used, unless only slaves with a mandatory byte can cause an In-Band Interrupt."]
267 #[inline(always)]
268 pub fn is_ack_with_mandatory(&self) -> bool {
269 *self == Ibiresp::AckWithMandatory
270 }
271 #[doc = "MANUAL: stop and wait for a decision using the IBIAckNack request"]
272 #[inline(always)]
273 pub fn is_manual(&self) -> bool {
274 *self == Ibiresp::Manual
275 }
276}
277#[doc = "Field `IBIRESP` writer - In-Band Interrupt (IBI) response"]
278pub type IbirespW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ibiresp, crate::Safe>;
279impl<'a, REG> IbirespW<'a, REG>
280where
281 REG: crate::Writable + crate::RegisterSpec,
282 REG::Ux: From<u8>,
283{
284 #[doc = "ACK: Acknowledge. A mandatory byte (or not) is decided by the Master In-band Interrupt Registry and Rules Register (MIBIRULES). To limit the maximum number of IBI bytes, configure the Read Termination field (MCTRL.RDTERM)."]
285 #[inline(always)]
286 pub fn ack(self) -> &'a mut crate::W<REG> {
287 self.variant(Ibiresp::Ack)
288 }
289 #[doc = "NACK: Not acknowledge"]
290 #[inline(always)]
291 pub fn nack(self) -> &'a mut crate::W<REG> {
292 self.variant(Ibiresp::Nack)
293 }
294 #[doc = "ACK_WITH_MANDATORY: Acknowledge with mandatory byte (ignores the MIBIRULES register). Acknowledge with mandatory byte should not be used, unless only slaves with a mandatory byte can cause an In-Band Interrupt."]
295 #[inline(always)]
296 pub fn ack_with_mandatory(self) -> &'a mut crate::W<REG> {
297 self.variant(Ibiresp::AckWithMandatory)
298 }
299 #[doc = "MANUAL: stop and wait for a decision using the IBIAckNack request"]
300 #[inline(always)]
301 pub fn manual(self) -> &'a mut crate::W<REG> {
302 self.variant(Ibiresp::Manual)
303 }
304}
305#[doc = "DIR\n\nValue on reset: 0"]
306#[cfg_attr(feature = "defmt", derive(defmt::Format))]
307#[derive(Clone, Copy, Debug, PartialEq, Eq)]
308pub enum Dir {
309 #[doc = "0: DIRWRITE: Write"]
310 Dirwrite = 0,
311 #[doc = "1: DIRREAD: Read"]
312 Dirread = 1,
313}
314impl From<Dir> for bool {
315 #[inline(always)]
316 fn from(variant: Dir) -> Self {
317 variant as u8 != 0
318 }
319}
320#[doc = "Field `DIR` reader - DIR"]
321pub type DirR = crate::BitReader<Dir>;
322impl DirR {
323 #[doc = "Get enumerated values variant"]
324 #[inline(always)]
325 pub const fn variant(&self) -> Dir {
326 match self.bits {
327 false => Dir::Dirwrite,
328 true => Dir::Dirread,
329 }
330 }
331 #[doc = "DIRWRITE: Write"]
332 #[inline(always)]
333 pub fn is_dirwrite(&self) -> bool {
334 *self == Dir::Dirwrite
335 }
336 #[doc = "DIRREAD: Read"]
337 #[inline(always)]
338 pub fn is_dirread(&self) -> bool {
339 *self == Dir::Dirread
340 }
341}
342#[doc = "Field `DIR` writer - DIR"]
343pub type DirW<'a, REG> = crate::BitWriter<'a, REG, Dir>;
344impl<'a, REG> DirW<'a, REG>
345where
346 REG: crate::Writable + crate::RegisterSpec,
347{
348 #[doc = "DIRWRITE: Write"]
349 #[inline(always)]
350 pub fn dirwrite(self) -> &'a mut crate::W<REG> {
351 self.variant(Dir::Dirwrite)
352 }
353 #[doc = "DIRREAD: Read"]
354 #[inline(always)]
355 pub fn dirread(self) -> &'a mut crate::W<REG> {
356 self.variant(Dir::Dirread)
357 }
358}
359#[doc = "Field `ADDR` reader - ADDR"]
360pub type AddrR = crate::FieldReader;
361#[doc = "Field `ADDR` writer - ADDR"]
362pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
363#[doc = "Field `RDTERM` reader - Read terminate"]
364pub type RdtermR = crate::FieldReader;
365#[doc = "Field `RDTERM` writer - Read terminate"]
366pub type RdtermW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
367impl R {
368 #[doc = "Bits 0:2 - Request"]
369 #[inline(always)]
370 pub fn request(&self) -> RequestR {
371 RequestR::new((self.bits & 7) as u8)
372 }
373 #[doc = "Bits 4:5 - Bus type with START"]
374 #[inline(always)]
375 pub fn type_(&self) -> TypeR {
376 TypeR::new(((self.bits >> 4) & 3) as u8)
377 }
378 #[doc = "Bits 6:7 - In-Band Interrupt (IBI) response"]
379 #[inline(always)]
380 pub fn ibiresp(&self) -> IbirespR {
381 IbirespR::new(((self.bits >> 6) & 3) as u8)
382 }
383 #[doc = "Bit 8 - DIR"]
384 #[inline(always)]
385 pub fn dir(&self) -> DirR {
386 DirR::new(((self.bits >> 8) & 1) != 0)
387 }
388 #[doc = "Bits 9:15 - ADDR"]
389 #[inline(always)]
390 pub fn addr(&self) -> AddrR {
391 AddrR::new(((self.bits >> 9) & 0x7f) as u8)
392 }
393 #[doc = "Bits 16:23 - Read terminate"]
394 #[inline(always)]
395 pub fn rdterm(&self) -> RdtermR {
396 RdtermR::new(((self.bits >> 16) & 0xff) as u8)
397 }
398}
399#[cfg(feature = "debug")]
400impl core::fmt::Debug for R {
401 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
402 f.debug_struct("MCTRL")
403 .field("request", &self.request())
404 .field("type_", &self.type_())
405 .field("ibiresp", &self.ibiresp())
406 .field("dir", &self.dir())
407 .field("addr", &self.addr())
408 .field("rdterm", &self.rdterm())
409 .finish()
410 }
411}
412impl W {
413 #[doc = "Bits 0:2 - Request"]
414 #[inline(always)]
415 pub fn request(&mut self) -> RequestW<MctrlSpec> {
416 RequestW::new(self, 0)
417 }
418 #[doc = "Bits 4:5 - Bus type with START"]
419 #[inline(always)]
420 pub fn type_(&mut self) -> TypeW<MctrlSpec> {
421 TypeW::new(self, 4)
422 }
423 #[doc = "Bits 6:7 - In-Band Interrupt (IBI) response"]
424 #[inline(always)]
425 pub fn ibiresp(&mut self) -> IbirespW<MctrlSpec> {
426 IbirespW::new(self, 6)
427 }
428 #[doc = "Bit 8 - DIR"]
429 #[inline(always)]
430 pub fn dir(&mut self) -> DirW<MctrlSpec> {
431 DirW::new(self, 8)
432 }
433 #[doc = "Bits 9:15 - ADDR"]
434 #[inline(always)]
435 pub fn addr(&mut self) -> AddrW<MctrlSpec> {
436 AddrW::new(self, 9)
437 }
438 #[doc = "Bits 16:23 - Read terminate"]
439 #[inline(always)]
440 pub fn rdterm(&mut self) -> RdtermW<MctrlSpec> {
441 RdtermW::new(self, 16)
442 }
443}
444#[doc = "Master Main Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
445pub struct MctrlSpec;
446impl crate::RegisterSpec for MctrlSpec {
447 type Ux = u32;
448}
449#[doc = "`read()` method returns [`mctrl::R`](R) reader structure"]
450impl crate::Readable for MctrlSpec {}
451#[doc = "`write(|w| ..)` method takes [`mctrl::W`](W) writer structure"]
452impl crate::Writable for MctrlSpec {
453 type Safety = crate::Unsafe;
454 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
455 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
456}
457#[doc = "`reset()` method sets MCTRL to value 0"]
458impl crate::Resettable for MctrlSpec {
459 const RESET_VALUE: u32 = 0;
460}