mimxrt685s_pac/usbphy/
debug0_tog.rs1#[doc = "Register `DEBUG0_TOG` reader"]
2pub type R = crate::R<Debug0TogSpec>;
3#[doc = "Register `DEBUG0_TOG` writer"]
4pub type W = crate::W<Debug0TogSpec>;
5#[doc = "Field `DEBUG_INTERFACE_HOLD` reader - Use holding registers to assist in timing for external UTMI interface."]
6pub type DebugInterfaceHoldR = crate::BitReader;
7#[doc = "Field `DEBUG_INTERFACE_HOLD` writer - Use holding registers to assist in timing for external UTMI interface."]
8pub type DebugInterfaceHoldW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `HSTPULLDOWN` reader - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG\\[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line"]
10pub type HstpulldownR = crate::FieldReader;
11#[doc = "Field `HSTPULLDOWN` writer - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG\\[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line"]
12pub type HstpulldownW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `ENHSTPULLDOWN` reader - This bit field selects host pulldown overdrive mode"]
14pub type EnhstpulldownR = crate::FieldReader;
15#[doc = "Field `ENHSTPULLDOWN` writer - This bit field selects host pulldown overdrive mode"]
16pub type EnhstpulldownW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `TX2RXCOUNT` reader - Delay in between the end of transmit to the beginning of receive"]
18pub type Tx2rxcountR = crate::FieldReader;
19#[doc = "Field `TX2RXCOUNT` writer - Delay in between the end of transmit to the beginning of receive"]
20pub type Tx2rxcountW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21#[doc = "Field `ENTX2RXCOUNT` reader - Set this bit to allow a countdown to transition in between TX and RX."]
22pub type Entx2rxcountR = crate::BitReader;
23#[doc = "Field `ENTX2RXCOUNT` writer - Set this bit to allow a countdown to transition in between TX and RX."]
24pub type Entx2rxcountW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SQUELCHRESETCOUNT` reader - Delay in between the detection of squelch to the reset of high-speed RX."]
26pub type SquelchresetcountR = crate::FieldReader;
27#[doc = "Field `SQUELCHRESETCOUNT` writer - Delay in between the detection of squelch to the reset of high-speed RX."]
28pub type SquelchresetcountW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
29#[doc = "Field `ENSQUELCHRESET` reader - Set bit to allow squelch to reset high-speed receive."]
30pub type EnsquelchresetR = crate::BitReader;
31#[doc = "Field `ENSQUELCHRESET` writer - Set bit to allow squelch to reset high-speed receive."]
32pub type EnsquelchresetW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SQUELCHRESETLENGTH` reader - Duration of RESET in terms of the number of 480-MHz cycles."]
34pub type SquelchresetlengthR = crate::FieldReader;
35#[doc = "Field `SQUELCHRESETLENGTH` writer - Duration of RESET in terms of the number of 480-MHz cycles."]
36pub type SquelchresetlengthW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
37#[doc = "Field `HOST_RESUME_DEBUG` reader - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."]
38pub type HostResumeDebugR = crate::BitReader;
39#[doc = "Field `HOST_RESUME_DEBUG` writer - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."]
40pub type HostResumeDebugW<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CLKGATE` reader - Gate Test Clocks"]
42pub type ClkgateR = crate::BitReader;
43#[doc = "Field `CLKGATE` writer - Gate Test Clocks"]
44pub type ClkgateW<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46 #[doc = "Bit 1 - Use holding registers to assist in timing for external UTMI interface."]
47 #[inline(always)]
48 pub fn debug_interface_hold(&self) -> DebugInterfaceHoldR {
49 DebugInterfaceHoldR::new(((self.bits >> 1) & 1) != 0)
50 }
51 #[doc = "Bits 2:3 - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG\\[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line"]
52 #[inline(always)]
53 pub fn hstpulldown(&self) -> HstpulldownR {
54 HstpulldownR::new(((self.bits >> 2) & 3) as u8)
55 }
56 #[doc = "Bits 4:5 - This bit field selects host pulldown overdrive mode"]
57 #[inline(always)]
58 pub fn enhstpulldown(&self) -> EnhstpulldownR {
59 EnhstpulldownR::new(((self.bits >> 4) & 3) as u8)
60 }
61 #[doc = "Bits 8:11 - Delay in between the end of transmit to the beginning of receive"]
62 #[inline(always)]
63 pub fn tx2rxcount(&self) -> Tx2rxcountR {
64 Tx2rxcountR::new(((self.bits >> 8) & 0x0f) as u8)
65 }
66 #[doc = "Bit 12 - Set this bit to allow a countdown to transition in between TX and RX."]
67 #[inline(always)]
68 pub fn entx2rxcount(&self) -> Entx2rxcountR {
69 Entx2rxcountR::new(((self.bits >> 12) & 1) != 0)
70 }
71 #[doc = "Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX."]
72 #[inline(always)]
73 pub fn squelchresetcount(&self) -> SquelchresetcountR {
74 SquelchresetcountR::new(((self.bits >> 16) & 0x1f) as u8)
75 }
76 #[doc = "Bit 24 - Set bit to allow squelch to reset high-speed receive."]
77 #[inline(always)]
78 pub fn ensquelchreset(&self) -> EnsquelchresetR {
79 EnsquelchresetR::new(((self.bits >> 24) & 1) != 0)
80 }
81 #[doc = "Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles."]
82 #[inline(always)]
83 pub fn squelchresetlength(&self) -> SquelchresetlengthR {
84 SquelchresetlengthR::new(((self.bits >> 25) & 0x0f) as u8)
85 }
86 #[doc = "Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."]
87 #[inline(always)]
88 pub fn host_resume_debug(&self) -> HostResumeDebugR {
89 HostResumeDebugR::new(((self.bits >> 29) & 1) != 0)
90 }
91 #[doc = "Bit 30 - Gate Test Clocks"]
92 #[inline(always)]
93 pub fn clkgate(&self) -> ClkgateR {
94 ClkgateR::new(((self.bits >> 30) & 1) != 0)
95 }
96}
97#[cfg(feature = "debug")]
98impl core::fmt::Debug for R {
99 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
100 f.debug_struct("DEBUG0_TOG")
101 .field("debug_interface_hold", &self.debug_interface_hold())
102 .field("hstpulldown", &self.hstpulldown())
103 .field("enhstpulldown", &self.enhstpulldown())
104 .field("tx2rxcount", &self.tx2rxcount())
105 .field("entx2rxcount", &self.entx2rxcount())
106 .field("squelchresetcount", &self.squelchresetcount())
107 .field("ensquelchreset", &self.ensquelchreset())
108 .field("squelchresetlength", &self.squelchresetlength())
109 .field("host_resume_debug", &self.host_resume_debug())
110 .field("clkgate", &self.clkgate())
111 .finish()
112 }
113}
114impl W {
115 #[doc = "Bit 1 - Use holding registers to assist in timing for external UTMI interface."]
116 #[inline(always)]
117 pub fn debug_interface_hold(&mut self) -> DebugInterfaceHoldW<Debug0TogSpec> {
118 DebugInterfaceHoldW::new(self, 1)
119 }
120 #[doc = "Bits 2:3 - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG\\[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line"]
121 #[inline(always)]
122 pub fn hstpulldown(&mut self) -> HstpulldownW<Debug0TogSpec> {
123 HstpulldownW::new(self, 2)
124 }
125 #[doc = "Bits 4:5 - This bit field selects host pulldown overdrive mode"]
126 #[inline(always)]
127 pub fn enhstpulldown(&mut self) -> EnhstpulldownW<Debug0TogSpec> {
128 EnhstpulldownW::new(self, 4)
129 }
130 #[doc = "Bits 8:11 - Delay in between the end of transmit to the beginning of receive"]
131 #[inline(always)]
132 pub fn tx2rxcount(&mut self) -> Tx2rxcountW<Debug0TogSpec> {
133 Tx2rxcountW::new(self, 8)
134 }
135 #[doc = "Bit 12 - Set this bit to allow a countdown to transition in between TX and RX."]
136 #[inline(always)]
137 pub fn entx2rxcount(&mut self) -> Entx2rxcountW<Debug0TogSpec> {
138 Entx2rxcountW::new(self, 12)
139 }
140 #[doc = "Bits 16:20 - Delay in between the detection of squelch to the reset of high-speed RX."]
141 #[inline(always)]
142 pub fn squelchresetcount(&mut self) -> SquelchresetcountW<Debug0TogSpec> {
143 SquelchresetcountW::new(self, 16)
144 }
145 #[doc = "Bit 24 - Set bit to allow squelch to reset high-speed receive."]
146 #[inline(always)]
147 pub fn ensquelchreset(&mut self) -> EnsquelchresetW<Debug0TogSpec> {
148 EnsquelchresetW::new(self, 24)
149 }
150 #[doc = "Bits 25:28 - Duration of RESET in terms of the number of 480-MHz cycles."]
151 #[inline(always)]
152 pub fn squelchresetlength(&mut self) -> SquelchresetlengthW<Debug0TogSpec> {
153 SquelchresetlengthW::new(self, 25)
154 }
155 #[doc = "Bit 29 - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1."]
156 #[inline(always)]
157 pub fn host_resume_debug(&mut self) -> HostResumeDebugW<Debug0TogSpec> {
158 HostResumeDebugW::new(self, 29)
159 }
160 #[doc = "Bit 30 - Gate Test Clocks"]
161 #[inline(always)]
162 pub fn clkgate(&mut self) -> ClkgateW<Debug0TogSpec> {
163 ClkgateW::new(self, 30)
164 }
165}
166#[doc = "USB PHY Debug Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`debug0_tog::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`debug0_tog::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
167pub struct Debug0TogSpec;
168impl crate::RegisterSpec for Debug0TogSpec {
169 type Ux = u32;
170}
171#[doc = "`read()` method returns [`debug0_tog::R`](R) reader structure"]
172impl crate::Readable for Debug0TogSpec {}
173#[doc = "`write(|w| ..)` method takes [`debug0_tog::W`](W) writer structure"]
174impl crate::Writable for Debug0TogSpec {
175 type Safety = crate::Unsafe;
176 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
177 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
178}
179#[doc = "`reset()` method sets DEBUG0_TOG to value 0x7f18_0000"]
180impl crate::Resettable for Debug0TogSpec {
181 const RESET_VALUE: u32 = 0x7f18_0000;
182}