mimxrt685s_pac/usbhsh/
usbcmd.rs

1#[doc = "Register `USBCMD` reader"]
2pub type R = crate::R<UsbcmdSpec>;
3#[doc = "Register `USBCMD` writer"]
4pub type W = crate::W<UsbcmdSpec>;
5#[doc = "Field `RS` reader - Run/Stop: 1b = Run."]
6pub type RsR = crate::BitReader;
7#[doc = "Field `RS` writer - Run/Stop: 1b = Run."]
8pub type RsW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `HCRESET` reader - Host Controller Reset: This control bit is used by the software to reset the host controller."]
10pub type HcresetR = crate::BitReader;
11#[doc = "Field `HCRESET` writer - Host Controller Reset: This control bit is used by the software to reset the host controller."]
12pub type HcresetW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FLS` reader - Frame List Size: This field specifies the size of the frame list."]
14pub type FlsR = crate::FieldReader;
15#[doc = "Field `FLS` writer - Frame List Size: This field specifies the size of the frame list."]
16pub type FlsW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `LHCR` reader - Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports."]
18pub type LhcrR = crate::BitReader;
19#[doc = "Field `LHCR` writer - Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports."]
20pub type LhcrW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ATL_EN` reader - ATL List enabled."]
22pub type AtlEnR = crate::BitReader;
23#[doc = "Field `ATL_EN` writer - ATL List enabled."]
24pub type AtlEnW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ISO_EN` reader - ISO List enabled."]
26pub type IsoEnR = crate::BitReader;
27#[doc = "Field `ISO_EN` writer - ISO List enabled."]
28pub type IsoEnW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `INT_EN` reader - INT List enabled."]
30pub type IntEnR = crate::BitReader;
31#[doc = "Field `INT_EN` writer - INT List enabled."]
32pub type IntEnW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `HIRD` reader - Host-Initiated Resume Duration."]
34pub type HirdR = crate::FieldReader;
35#[doc = "Field `HIRD` writer - Host-Initiated Resume Duration."]
36pub type HirdW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
37impl R {
38    #[doc = "Bit 0 - Run/Stop: 1b = Run."]
39    #[inline(always)]
40    pub fn rs(&self) -> RsR {
41        RsR::new((self.bits & 1) != 0)
42    }
43    #[doc = "Bit 1 - Host Controller Reset: This control bit is used by the software to reset the host controller."]
44    #[inline(always)]
45    pub fn hcreset(&self) -> HcresetR {
46        HcresetR::new(((self.bits >> 1) & 1) != 0)
47    }
48    #[doc = "Bits 2:3 - Frame List Size: This field specifies the size of the frame list."]
49    #[inline(always)]
50    pub fn fls(&self) -> FlsR {
51        FlsR::new(((self.bits >> 2) & 3) as u8)
52    }
53    #[doc = "Bit 7 - Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports."]
54    #[inline(always)]
55    pub fn lhcr(&self) -> LhcrR {
56        LhcrR::new(((self.bits >> 7) & 1) != 0)
57    }
58    #[doc = "Bit 8 - ATL List enabled."]
59    #[inline(always)]
60    pub fn atl_en(&self) -> AtlEnR {
61        AtlEnR::new(((self.bits >> 8) & 1) != 0)
62    }
63    #[doc = "Bit 9 - ISO List enabled."]
64    #[inline(always)]
65    pub fn iso_en(&self) -> IsoEnR {
66        IsoEnR::new(((self.bits >> 9) & 1) != 0)
67    }
68    #[doc = "Bit 10 - INT List enabled."]
69    #[inline(always)]
70    pub fn int_en(&self) -> IntEnR {
71        IntEnR::new(((self.bits >> 10) & 1) != 0)
72    }
73    #[doc = "Bits 24:27 - Host-Initiated Resume Duration."]
74    #[inline(always)]
75    pub fn hird(&self) -> HirdR {
76        HirdR::new(((self.bits >> 24) & 0x0f) as u8)
77    }
78}
79#[cfg(feature = "debug")]
80impl core::fmt::Debug for R {
81    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
82        f.debug_struct("USBCMD")
83            .field("rs", &self.rs())
84            .field("hcreset", &self.hcreset())
85            .field("fls", &self.fls())
86            .field("lhcr", &self.lhcr())
87            .field("atl_en", &self.atl_en())
88            .field("iso_en", &self.iso_en())
89            .field("int_en", &self.int_en())
90            .field("hird", &self.hird())
91            .finish()
92    }
93}
94impl W {
95    #[doc = "Bit 0 - Run/Stop: 1b = Run."]
96    #[inline(always)]
97    pub fn rs(&mut self) -> RsW<UsbcmdSpec> {
98        RsW::new(self, 0)
99    }
100    #[doc = "Bit 1 - Host Controller Reset: This control bit is used by the software to reset the host controller."]
101    #[inline(always)]
102    pub fn hcreset(&mut self) -> HcresetW<UsbcmdSpec> {
103        HcresetW::new(self, 1)
104    }
105    #[doc = "Bits 2:3 - Frame List Size: This field specifies the size of the frame list."]
106    #[inline(always)]
107    pub fn fls(&mut self) -> FlsW<UsbcmdSpec> {
108        FlsW::new(self, 2)
109    }
110    #[doc = "Bit 7 - Light Host Controller Reset: This bit allows the driver software to reset the host controller without affecting the state of the ports."]
111    #[inline(always)]
112    pub fn lhcr(&mut self) -> LhcrW<UsbcmdSpec> {
113        LhcrW::new(self, 7)
114    }
115    #[doc = "Bit 8 - ATL List enabled."]
116    #[inline(always)]
117    pub fn atl_en(&mut self) -> AtlEnW<UsbcmdSpec> {
118        AtlEnW::new(self, 8)
119    }
120    #[doc = "Bit 9 - ISO List enabled."]
121    #[inline(always)]
122    pub fn iso_en(&mut self) -> IsoEnW<UsbcmdSpec> {
123        IsoEnW::new(self, 9)
124    }
125    #[doc = "Bit 10 - INT List enabled."]
126    #[inline(always)]
127    pub fn int_en(&mut self) -> IntEnW<UsbcmdSpec> {
128        IntEnW::new(self, 10)
129    }
130    #[doc = "Bits 24:27 - Host-Initiated Resume Duration."]
131    #[inline(always)]
132    pub fn hird(&mut self) -> HirdW<UsbcmdSpec> {
133        HirdW::new(self, 24)
134    }
135}
136#[doc = "USB Command register\n\nYou can [`read`](crate::Reg::read) this register and get [`usbcmd::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbcmd::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct UsbcmdSpec;
138impl crate::RegisterSpec for UsbcmdSpec {
139    type Ux = u32;
140}
141#[doc = "`read()` method returns [`usbcmd::R`](R) reader structure"]
142impl crate::Readable for UsbcmdSpec {}
143#[doc = "`write(|w| ..)` method takes [`usbcmd::W`](W) writer structure"]
144impl crate::Writable for UsbcmdSpec {
145    type Safety = crate::Unsafe;
146    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
147    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148}
149#[doc = "`reset()` method sets USBCMD to value 0"]
150impl crate::Resettable for UsbcmdSpec {
151    const RESET_VALUE: u32 = 0;
152}
mimxrt685s_pac/usbhsh/usbcmd.rs

mimxrt685s_pac/usbhsh/
usbcmd.rs
