mimxrt685s_pac/usart0/
intenclr.rs

1#[doc = "Register `INTENCLR` writer"]
2pub type W = crate::W<IntenclrSpec>;
3#[doc = "Field `TXIDLECLR` writer - Writing 1 clears the corresponding bit in the INTENSET register."]
4pub type TxidleclrW<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `DELTACTSCLR` writer - Writing 1 clears the corresponding bit in the INTENSET register."]
6pub type DeltactsclrW<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `TXDISCLR` writer - Writing 1 clears the corresponding bit in the INTENSET register."]
8pub type TxdisclrW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `DELTARXBRKCLR` writer - Writing 1 clears the corresponding bit in the INTENSET register."]
10pub type DeltarxbrkclrW<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `STARTCLR` writer - Writing 1 clears the corresponding bit in the INTENSET register."]
12pub type StartclrW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FRAMERRCLR` writer - Writing 1 clears the corresponding bit in the INTENSET register."]
14pub type FramerrclrW<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `PARITYERRCLR` writer - Writing 1 clears the corresponding bit in the INTENSET register."]
16pub type ParityerrclrW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RXNOISECLR` writer - Writing 1 clears the corresponding bit in the INTENSET register."]
18pub type RxnoiseclrW<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `ABERRCLR` writer - Writing 1 clears the corresponding bit in the INTENSET register."]
20pub type AberrclrW<'a, REG> = crate::BitWriter<'a, REG>;
21#[cfg(feature = "debug")]
22impl core::fmt::Debug for crate::generic::Reg<IntenclrSpec> {
23    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
24        write!(f, "(not readable)")
25    }
26}
27impl W {
28    #[doc = "Bit 3 - Writing 1 clears the corresponding bit in the INTENSET register."]
29    #[inline(always)]
30    pub fn txidleclr(&mut self) -> TxidleclrW<IntenclrSpec> {
31        TxidleclrW::new(self, 3)
32    }
33    #[doc = "Bit 5 - Writing 1 clears the corresponding bit in the INTENSET register."]
34    #[inline(always)]
35    pub fn deltactsclr(&mut self) -> DeltactsclrW<IntenclrSpec> {
36        DeltactsclrW::new(self, 5)
37    }
38    #[doc = "Bit 6 - Writing 1 clears the corresponding bit in the INTENSET register."]
39    #[inline(always)]
40    pub fn txdisclr(&mut self) -> TxdisclrW<IntenclrSpec> {
41        TxdisclrW::new(self, 6)
42    }
43    #[doc = "Bit 11 - Writing 1 clears the corresponding bit in the INTENSET register."]
44    #[inline(always)]
45    pub fn deltarxbrkclr(&mut self) -> DeltarxbrkclrW<IntenclrSpec> {
46        DeltarxbrkclrW::new(self, 11)
47    }
48    #[doc = "Bit 12 - Writing 1 clears the corresponding bit in the INTENSET register."]
49    #[inline(always)]
50    pub fn startclr(&mut self) -> StartclrW<IntenclrSpec> {
51        StartclrW::new(self, 12)
52    }
53    #[doc = "Bit 13 - Writing 1 clears the corresponding bit in the INTENSET register."]
54    #[inline(always)]
55    pub fn framerrclr(&mut self) -> FramerrclrW<IntenclrSpec> {
56        FramerrclrW::new(self, 13)
57    }
58    #[doc = "Bit 14 - Writing 1 clears the corresponding bit in the INTENSET register."]
59    #[inline(always)]
60    pub fn parityerrclr(&mut self) -> ParityerrclrW<IntenclrSpec> {
61        ParityerrclrW::new(self, 14)
62    }
63    #[doc = "Bit 15 - Writing 1 clears the corresponding bit in the INTENSET register."]
64    #[inline(always)]
65    pub fn rxnoiseclr(&mut self) -> RxnoiseclrW<IntenclrSpec> {
66        RxnoiseclrW::new(self, 15)
67    }
68    #[doc = "Bit 16 - Writing 1 clears the corresponding bit in the INTENSET register."]
69    #[inline(always)]
70    pub fn aberrclr(&mut self) -> AberrclrW<IntenclrSpec> {
71        AberrclrW::new(self, 16)
72    }
73}
74#[doc = "Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
75pub struct IntenclrSpec;
76impl crate::RegisterSpec for IntenclrSpec {
77    type Ux = u32;
78}
79#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
80impl crate::Writable for IntenclrSpec {
81    type Safety = crate::Unsafe;
82    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
83    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
84}
85#[doc = "`reset()` method sets INTENCLR to value 0"]
86impl crate::Resettable for IntenclrSpec {
87    const RESET_VALUE: u32 = 0;
88}
mimxrt685s_pac/usart0/intenclr.rs

mimxrt685s_pac/usart0/
intenclr.rs
