mimxrt685s_pac/trng/
mctl.rs

1#[doc = "Register `MCTL` reader"]
2pub type R = crate::R<MctlSpec>;
3#[doc = "Register `MCTL` writer"]
4pub type W = crate::W<MctlSpec>;
5#[doc = "Sample Mode\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum SampMode {
10    #[doc = "0: use Von Neumann data into both Entropy shifter and Statistical Checker"]
11    SampMode0 = 0,
12    #[doc = "1: use raw data into both Entropy shifter and Statistical Checker"]
13    SampMode1 = 1,
14    #[doc = "2: use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker"]
15    SampMode2 = 2,
16    #[doc = "3: undefined/reserved."]
17    SampMode3 = 3,
18}
19impl From<SampMode> for u8 {
20    #[inline(always)]
21    fn from(variant: SampMode) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for SampMode {
26    type Ux = u8;
27}
28impl crate::IsEnum for SampMode {}
29#[doc = "Field `SAMP_MODE` reader - Sample Mode"]
30pub type SampModeR = crate::FieldReader<SampMode>;
31impl SampModeR {
32    #[doc = "Get enumerated values variant"]
33    #[inline(always)]
34    pub const fn variant(&self) -> SampMode {
35        match self.bits {
36            0 => SampMode::SampMode0,
37            1 => SampMode::SampMode1,
38            2 => SampMode::SampMode2,
39            3 => SampMode::SampMode3,
40            _ => unreachable!(),
41        }
42    }
43    #[doc = "use Von Neumann data into both Entropy shifter and Statistical Checker"]
44    #[inline(always)]
45    pub fn is_samp_mode_0(&self) -> bool {
46        *self == SampMode::SampMode0
47    }
48    #[doc = "use raw data into both Entropy shifter and Statistical Checker"]
49    #[inline(always)]
50    pub fn is_samp_mode_1(&self) -> bool {
51        *self == SampMode::SampMode1
52    }
53    #[doc = "use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker"]
54    #[inline(always)]
55    pub fn is_samp_mode_2(&self) -> bool {
56        *self == SampMode::SampMode2
57    }
58    #[doc = "undefined/reserved."]
59    #[inline(always)]
60    pub fn is_samp_mode_3(&self) -> bool {
61        *self == SampMode::SampMode3
62    }
63}
64#[doc = "Field `SAMP_MODE` writer - Sample Mode"]
65pub type SampModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, SampMode, crate::Safe>;
66impl<'a, REG> SampModeW<'a, REG>
67where
68    REG: crate::Writable + crate::RegisterSpec,
69    REG::Ux: From<u8>,
70{
71    #[doc = "use Von Neumann data into both Entropy shifter and Statistical Checker"]
72    #[inline(always)]
73    pub fn samp_mode_0(self) -> &'a mut crate::W<REG> {
74        self.variant(SampMode::SampMode0)
75    }
76    #[doc = "use raw data into both Entropy shifter and Statistical Checker"]
77    #[inline(always)]
78    pub fn samp_mode_1(self) -> &'a mut crate::W<REG> {
79        self.variant(SampMode::SampMode1)
80    }
81    #[doc = "use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker"]
82    #[inline(always)]
83    pub fn samp_mode_2(self) -> &'a mut crate::W<REG> {
84        self.variant(SampMode::SampMode2)
85    }
86    #[doc = "undefined/reserved."]
87    #[inline(always)]
88    pub fn samp_mode_3(self) -> &'a mut crate::W<REG> {
89        self.variant(SampMode::SampMode3)
90    }
91}
92#[doc = "Oscillator Divide\n\nValue on reset: 0"]
93#[cfg_attr(feature = "defmt", derive(defmt::Format))]
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95#[repr(u8)]
96pub enum OscDiv {
97    #[doc = "0: use ring oscillator with no divide"]
98    OscDiv0 = 0,
99    #[doc = "1: use ring oscillator divided-by-2"]
100    OscDiv1 = 1,
101    #[doc = "2: use ring oscillator divided-by-4"]
102    OscDiv2 = 2,
103    #[doc = "3: use ring oscillator divided-by-8"]
104    OscDiv3 = 3,
105}
106impl From<OscDiv> for u8 {
107    #[inline(always)]
108    fn from(variant: OscDiv) -> Self {
109        variant as _
110    }
111}
112impl crate::FieldSpec for OscDiv {
113    type Ux = u8;
114}
115impl crate::IsEnum for OscDiv {}
116#[doc = "Field `OSC_DIV` reader - Oscillator Divide"]
117pub type OscDivR = crate::FieldReader<OscDiv>;
118impl OscDivR {
119    #[doc = "Get enumerated values variant"]
120    #[inline(always)]
121    pub const fn variant(&self) -> OscDiv {
122        match self.bits {
123            0 => OscDiv::OscDiv0,
124            1 => OscDiv::OscDiv1,
125            2 => OscDiv::OscDiv2,
126            3 => OscDiv::OscDiv3,
127            _ => unreachable!(),
128        }
129    }
130    #[doc = "use ring oscillator with no divide"]
131    #[inline(always)]
132    pub fn is_osc_div_0(&self) -> bool {
133        *self == OscDiv::OscDiv0
134    }
135    #[doc = "use ring oscillator divided-by-2"]
136    #[inline(always)]
137    pub fn is_osc_div_1(&self) -> bool {
138        *self == OscDiv::OscDiv1
139    }
140    #[doc = "use ring oscillator divided-by-4"]
141    #[inline(always)]
142    pub fn is_osc_div_2(&self) -> bool {
143        *self == OscDiv::OscDiv2
144    }
145    #[doc = "use ring oscillator divided-by-8"]
146    #[inline(always)]
147    pub fn is_osc_div_3(&self) -> bool {
148        *self == OscDiv::OscDiv3
149    }
150}
151#[doc = "Field `OSC_DIV` writer - Oscillator Divide"]
152pub type OscDivW<'a, REG> = crate::FieldWriter<'a, REG, 2, OscDiv, crate::Safe>;
153impl<'a, REG> OscDivW<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156    REG::Ux: From<u8>,
157{
158    #[doc = "use ring oscillator with no divide"]
159    #[inline(always)]
160    pub fn osc_div_0(self) -> &'a mut crate::W<REG> {
161        self.variant(OscDiv::OscDiv0)
162    }
163    #[doc = "use ring oscillator divided-by-2"]
164    #[inline(always)]
165    pub fn osc_div_1(self) -> &'a mut crate::W<REG> {
166        self.variant(OscDiv::OscDiv1)
167    }
168    #[doc = "use ring oscillator divided-by-4"]
169    #[inline(always)]
170    pub fn osc_div_2(self) -> &'a mut crate::W<REG> {
171        self.variant(OscDiv::OscDiv2)
172    }
173    #[doc = "use ring oscillator divided-by-8"]
174    #[inline(always)]
175    pub fn osc_div_3(self) -> &'a mut crate::W<REG> {
176        self.variant(OscDiv::OscDiv3)
177    }
178}
179#[doc = "Field `TRNG_ACC` reader - TRNG Access Mode"]
180pub type TrngAccR = crate::BitReader;
181#[doc = "Field `TRNG_ACC` writer - TRNG Access Mode"]
182pub type TrngAccW<'a, REG> = crate::BitWriter<'a, REG>;
183#[doc = "Field `RST_DEF` writer - Reset Defaults"]
184pub type RstDefW<'a, REG> = crate::BitWriter<'a, REG>;
185#[doc = "Field `FOR_SCLK` reader - Force System Clock"]
186pub type ForSclkR = crate::BitReader;
187#[doc = "Field `FOR_SCLK` writer - Force System Clock"]
188pub type ForSclkW<'a, REG> = crate::BitWriter<'a, REG>;
189#[doc = "Field `FCT_FAIL` reader - Read only: Frequency Count Fail"]
190pub type FctFailR = crate::BitReader;
191#[doc = "Field `FCT_VAL` reader - Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT."]
192pub type FctValR = crate::BitReader;
193#[doc = "Field `ENT_VAL` reader - Read only: Entropy Valid"]
194pub type EntValR = crate::BitReader;
195#[doc = "Field `TST_OUT` reader - Read only: Test point inside ring oscillator."]
196pub type TstOutR = crate::BitReader;
197#[doc = "Field `ERR` reader - Read: Error status"]
198pub type ErrR = crate::BitReader;
199#[doc = "Field `ERR` writer - Read: Error status"]
200pub type ErrW<'a, REG> = crate::BitWriter1C<'a, REG>;
201#[doc = "Field `TSTOP_OK` reader - TRNG_OK_TO_STOP"]
202pub type TstopOkR = crate::BitReader;
203#[doc = "Field `PRGM` reader - Programming Mode Select"]
204pub type PrgmR = crate::BitReader;
205#[doc = "Field `PRGM` writer - Programming Mode Select"]
206pub type PrgmW<'a, REG> = crate::BitWriter<'a, REG>;
207impl R {
208    #[doc = "Bits 0:1 - Sample Mode"]
209    #[inline(always)]
210    pub fn samp_mode(&self) -> SampModeR {
211        SampModeR::new((self.bits & 3) as u8)
212    }
213    #[doc = "Bits 2:3 - Oscillator Divide"]
214    #[inline(always)]
215    pub fn osc_div(&self) -> OscDivR {
216        OscDivR::new(((self.bits >> 2) & 3) as u8)
217    }
218    #[doc = "Bit 5 - TRNG Access Mode"]
219    #[inline(always)]
220    pub fn trng_acc(&self) -> TrngAccR {
221        TrngAccR::new(((self.bits >> 5) & 1) != 0)
222    }
223    #[doc = "Bit 7 - Force System Clock"]
224    #[inline(always)]
225    pub fn for_sclk(&self) -> ForSclkR {
226        ForSclkR::new(((self.bits >> 7) & 1) != 0)
227    }
228    #[doc = "Bit 8 - Read only: Frequency Count Fail"]
229    #[inline(always)]
230    pub fn fct_fail(&self) -> FctFailR {
231        FctFailR::new(((self.bits >> 8) & 1) != 0)
232    }
233    #[doc = "Bit 9 - Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT."]
234    #[inline(always)]
235    pub fn fct_val(&self) -> FctValR {
236        FctValR::new(((self.bits >> 9) & 1) != 0)
237    }
238    #[doc = "Bit 10 - Read only: Entropy Valid"]
239    #[inline(always)]
240    pub fn ent_val(&self) -> EntValR {
241        EntValR::new(((self.bits >> 10) & 1) != 0)
242    }
243    #[doc = "Bit 11 - Read only: Test point inside ring oscillator."]
244    #[inline(always)]
245    pub fn tst_out(&self) -> TstOutR {
246        TstOutR::new(((self.bits >> 11) & 1) != 0)
247    }
248    #[doc = "Bit 12 - Read: Error status"]
249    #[inline(always)]
250    pub fn err(&self) -> ErrR {
251        ErrR::new(((self.bits >> 12) & 1) != 0)
252    }
253    #[doc = "Bit 13 - TRNG_OK_TO_STOP"]
254    #[inline(always)]
255    pub fn tstop_ok(&self) -> TstopOkR {
256        TstopOkR::new(((self.bits >> 13) & 1) != 0)
257    }
258    #[doc = "Bit 16 - Programming Mode Select"]
259    #[inline(always)]
260    pub fn prgm(&self) -> PrgmR {
261        PrgmR::new(((self.bits >> 16) & 1) != 0)
262    }
263}
264#[cfg(feature = "debug")]
265impl core::fmt::Debug for R {
266    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
267        f.debug_struct("MCTL")
268            .field("samp_mode", &self.samp_mode())
269            .field("osc_div", &self.osc_div())
270            .field("trng_acc", &self.trng_acc())
271            .field("for_sclk", &self.for_sclk())
272            .field("fct_fail", &self.fct_fail())
273            .field("fct_val", &self.fct_val())
274            .field("ent_val", &self.ent_val())
275            .field("tst_out", &self.tst_out())
276            .field("err", &self.err())
277            .field("tstop_ok", &self.tstop_ok())
278            .field("prgm", &self.prgm())
279            .finish()
280    }
281}
282impl W {
283    #[doc = "Bits 0:1 - Sample Mode"]
284    #[inline(always)]
285    pub fn samp_mode(&mut self) -> SampModeW<MctlSpec> {
286        SampModeW::new(self, 0)
287    }
288    #[doc = "Bits 2:3 - Oscillator Divide"]
289    #[inline(always)]
290    pub fn osc_div(&mut self) -> OscDivW<MctlSpec> {
291        OscDivW::new(self, 2)
292    }
293    #[doc = "Bit 5 - TRNG Access Mode"]
294    #[inline(always)]
295    pub fn trng_acc(&mut self) -> TrngAccW<MctlSpec> {
296        TrngAccW::new(self, 5)
297    }
298    #[doc = "Bit 6 - Reset Defaults"]
299    #[inline(always)]
300    pub fn rst_def(&mut self) -> RstDefW<MctlSpec> {
301        RstDefW::new(self, 6)
302    }
303    #[doc = "Bit 7 - Force System Clock"]
304    #[inline(always)]
305    pub fn for_sclk(&mut self) -> ForSclkW<MctlSpec> {
306        ForSclkW::new(self, 7)
307    }
308    #[doc = "Bit 12 - Read: Error status"]
309    #[inline(always)]
310    pub fn err(&mut self) -> ErrW<MctlSpec> {
311        ErrW::new(self, 12)
312    }
313    #[doc = "Bit 16 - Programming Mode Select"]
314    #[inline(always)]
315    pub fn prgm(&mut self) -> PrgmW<MctlSpec> {
316        PrgmW::new(self, 16)
317    }
318}
319#[doc = "Miscellaneous Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mctl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mctl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
320pub struct MctlSpec;
321impl crate::RegisterSpec for MctlSpec {
322    type Ux = u32;
323}
324#[doc = "`read()` method returns [`mctl::R`](R) reader structure"]
325impl crate::Readable for MctlSpec {}
326#[doc = "`write(|w| ..)` method takes [`mctl::W`](W) writer structure"]
327impl crate::Writable for MctlSpec {
328    type Safety = crate::Unsafe;
329    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
330    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1000;
331}
332#[doc = "`reset()` method sets MCTL to value 0x0001_2001"]
333impl crate::Resettable for MctlSpec {
334    const RESET_VALUE: u32 = 0x0001_2001;
335}
mimxrt685s_pac/trng/mctl.rs

mimxrt685s_pac/trng/
mctl.rs
