mimxrt685s_pac/spi0/
intenclr.rs

1#[doc = "Register `INTENCLR` reader"]
2pub type R = crate::R<IntenclrSpec>;
3#[doc = "Register `INTENCLR` writer"]
4pub type W = crate::W<IntenclrSpec>;
5#[doc = "Field `SSAEN` reader - Writing 1 clears the corresponding bit in the INTENSET register."]
6pub type SsaenR = crate::BitReader;
7#[doc = "Field `SSAEN` writer - Writing 1 clears the corresponding bit in the INTENSET register."]
8pub type SsaenW<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `SSDEN` reader - Writing 1 clears the corresponding bit in the INTENSET register."]
10pub type SsdenR = crate::BitReader;
11#[doc = "Field `SSDEN` writer - Writing 1 clears the corresponding bit in the INTENSET register."]
12pub type SsdenW<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `MSTIDLE` reader - Writing 1 clears the corresponding bit in the INTENSET register."]
14pub type MstidleR = crate::BitReader;
15#[doc = "Field `MSTIDLE` writer - Writing 1 clears the corresponding bit in the INTENSET register."]
16pub type MstidleW<'a, REG> = crate::BitWriter1C<'a, REG>;
17impl R {
18    #[doc = "Bit 4 - Writing 1 clears the corresponding bit in the INTENSET register."]
19    #[inline(always)]
20    pub fn ssaen(&self) -> SsaenR {
21        SsaenR::new(((self.bits >> 4) & 1) != 0)
22    }
23    #[doc = "Bit 5 - Writing 1 clears the corresponding bit in the INTENSET register."]
24    #[inline(always)]
25    pub fn ssden(&self) -> SsdenR {
26        SsdenR::new(((self.bits >> 5) & 1) != 0)
27    }
28    #[doc = "Bit 8 - Writing 1 clears the corresponding bit in the INTENSET register."]
29    #[inline(always)]
30    pub fn mstidle(&self) -> MstidleR {
31        MstidleR::new(((self.bits >> 8) & 1) != 0)
32    }
33}
34#[cfg(feature = "debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("INTENCLR")
38            .field("ssaen", &self.ssaen())
39            .field("ssden", &self.ssden())
40            .field("mstidle", &self.mstidle())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bit 4 - Writing 1 clears the corresponding bit in the INTENSET register."]
46    #[inline(always)]
47    pub fn ssaen(&mut self) -> SsaenW<IntenclrSpec> {
48        SsaenW::new(self, 4)
49    }
50    #[doc = "Bit 5 - Writing 1 clears the corresponding bit in the INTENSET register."]
51    #[inline(always)]
52    pub fn ssden(&mut self) -> SsdenW<IntenclrSpec> {
53        SsdenW::new(self, 5)
54    }
55    #[doc = "Bit 8 - Writing 1 clears the corresponding bit in the INTENSET register."]
56    #[inline(always)]
57    pub fn mstidle(&mut self) -> MstidleW<IntenclrSpec> {
58        MstidleW::new(self, 8)
59    }
60}
61#[doc = "SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.\n\nYou can [`read`](crate::Reg::read) this register and get [`intenclr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct IntenclrSpec;
63impl crate::RegisterSpec for IntenclrSpec {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`intenclr::R`](R) reader structure"]
67impl crate::Readable for IntenclrSpec {}
68#[doc = "`write(|w| ..)` method takes [`intenclr::W`](W) writer structure"]
69impl crate::Writable for IntenclrSpec {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0130;
73}
74#[doc = "`reset()` method sets INTENCLR to value 0"]
75impl crate::Resettable for IntenclrSpec {
76    const RESET_VALUE: u32 = 0;
77}
mimxrt685s_pac/spi0/intenclr.rs

mimxrt685s_pac/spi0/
intenclr.rs
