mimxrt685s_pac/spi0/
div.rs

1#[doc = "Register `DIV` reader"]
2pub type R = crate::R<DivSpec>;
3#[doc = "Register `DIV` writer"]
4pub type W = crate::W<DivSpec>;
5#[doc = "Field `DIVVAL` reader - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536."]
6pub type DivvalR = crate::FieldReader<u16>;
7#[doc = "Field `DIVVAL` writer - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536."]
8pub type DivvalW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9impl R {
10    #[doc = "Bits 0:15 - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536."]
11    #[inline(always)]
12    pub fn divval(&self) -> DivvalR {
13        DivvalR::new((self.bits & 0xffff) as u16)
14    }
15}
16#[cfg(feature = "debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("DIV")
20            .field("divval", &self.divval())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 0:15 - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results in FCLK/65536."]
26    #[inline(always)]
27    pub fn divval(&mut self) -> DivvalW<DivSpec> {
28        DivvalW::new(self, 0)
29    }
30}
31#[doc = "SPI clock Divider\n\nYou can [`read`](crate::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32pub struct DivSpec;
33impl crate::RegisterSpec for DivSpec {
34    type Ux = u32;
35}
36#[doc = "`read()` method returns [`div::R`](R) reader structure"]
37impl crate::Readable for DivSpec {}
38#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"]
39impl crate::Writable for DivSpec {
40    type Safety = crate::Unsafe;
41    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
42    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
43}
44#[doc = "`reset()` method sets DIV to value 0"]
45impl crate::Resettable for DivSpec {
46    const RESET_VALUE: u32 = 0;
47}
mimxrt685s_pac/spi0/div.rs

mimxrt685s_pac/spi0/
div.rs
