1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Software reset control\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Swreset {
9 #[doc = "0: Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC."]
10 NotInReset = 0,
11 #[doc = "1: In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the RTC_OSC_PD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared."]
12 InReset = 1,
13}
14impl From<Swreset> for bool {
15 #[inline(always)]
16 fn from(variant: Swreset) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `SWRESET` reader - Software reset control"]
21pub type SwresetR = crate::BitReader<Swreset>;
22impl SwresetR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> Swreset {
26 match self.bits {
27 false => Swreset::NotInReset,
28 true => Swreset::InReset,
29 }
30 }
31 #[doc = "Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC."]
32 #[inline(always)]
33 pub fn is_not_in_reset(&self) -> bool {
34 *self == Swreset::NotInReset
35 }
36 #[doc = "In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the RTC_OSC_PD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared."]
37 #[inline(always)]
38 pub fn is_in_reset(&self) -> bool {
39 *self == Swreset::InReset
40 }
41}
42#[doc = "Field `SWRESET` writer - Software reset control"]
43pub type SwresetW<'a, REG> = crate::BitWriter<'a, REG, Swreset>;
44impl<'a, REG> SwresetW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC."]
49 #[inline(always)]
50 pub fn not_in_reset(self) -> &'a mut crate::W<REG> {
51 self.variant(Swreset::NotInReset)
52 }
53 #[doc = "In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the RTC_OSC_PD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared."]
54 #[inline(always)]
55 pub fn in_reset(self) -> &'a mut crate::W<REG> {
56 self.variant(Swreset::InReset)
57 }
58}
59#[doc = "RTC 1 Hz timer alarm flag status.\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Alarm1hz {
63 #[doc = "0: No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect."]
64 NoMatch = 0,
65 #[doc = "1: Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit."]
66 Match = 1,
67}
68impl From<Alarm1hz> for bool {
69 #[inline(always)]
70 fn from(variant: Alarm1hz) -> Self {
71 variant as u8 != 0
72 }
73}
74#[doc = "Field `ALARM1HZ` reader - RTC 1 Hz timer alarm flag status."]
75pub type Alarm1hzR = crate::BitReader<Alarm1hz>;
76impl Alarm1hzR {
77 #[doc = "Get enumerated values variant"]
78 #[inline(always)]
79 pub const fn variant(&self) -> Alarm1hz {
80 match self.bits {
81 false => Alarm1hz::NoMatch,
82 true => Alarm1hz::Match,
83 }
84 }
85 #[doc = "No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect."]
86 #[inline(always)]
87 pub fn is_no_match(&self) -> bool {
88 *self == Alarm1hz::NoMatch
89 }
90 #[doc = "Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit."]
91 #[inline(always)]
92 pub fn is_match(&self) -> bool {
93 *self == Alarm1hz::Match
94 }
95}
96#[doc = "Field `ALARM1HZ` writer - RTC 1 Hz timer alarm flag status."]
97pub type Alarm1hzW<'a, REG> = crate::BitWriter<'a, REG, Alarm1hz>;
98impl<'a, REG> Alarm1hzW<'a, REG>
99where
100 REG: crate::Writable + crate::RegisterSpec,
101{
102 #[doc = "No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect."]
103 #[inline(always)]
104 pub fn no_match(self) -> &'a mut crate::W<REG> {
105 self.variant(Alarm1hz::NoMatch)
106 }
107 #[doc = "Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit."]
108 #[inline(always)]
109 pub fn match_(self) -> &'a mut crate::W<REG> {
110 self.variant(Alarm1hz::Match)
111 }
112}
113#[doc = "RTC 1 kHz timer wake-up flag status.\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Wake1khz {
117 #[doc = "0: Run. The RTC 1 kHz timer is running. Writing a 0 has no effect."]
118 Run = 0,
119 #[doc = "1: Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit."]
120 TimeOut = 1,
121}
122impl From<Wake1khz> for bool {
123 #[inline(always)]
124 fn from(variant: Wake1khz) -> Self {
125 variant as u8 != 0
126 }
127}
128#[doc = "Field `WAKE1KHZ` reader - RTC 1 kHz timer wake-up flag status."]
129pub type Wake1khzR = crate::BitReader<Wake1khz>;
130impl Wake1khzR {
131 #[doc = "Get enumerated values variant"]
132 #[inline(always)]
133 pub const fn variant(&self) -> Wake1khz {
134 match self.bits {
135 false => Wake1khz::Run,
136 true => Wake1khz::TimeOut,
137 }
138 }
139 #[doc = "Run. The RTC 1 kHz timer is running. Writing a 0 has no effect."]
140 #[inline(always)]
141 pub fn is_run(&self) -> bool {
142 *self == Wake1khz::Run
143 }
144 #[doc = "Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit."]
145 #[inline(always)]
146 pub fn is_time_out(&self) -> bool {
147 *self == Wake1khz::TimeOut
148 }
149}
150#[doc = "Field `WAKE1KHZ` writer - RTC 1 kHz timer wake-up flag status."]
151pub type Wake1khzW<'a, REG> = crate::BitWriter<'a, REG, Wake1khz>;
152impl<'a, REG> Wake1khzW<'a, REG>
153where
154 REG: crate::Writable + crate::RegisterSpec,
155{
156 #[doc = "Run. The RTC 1 kHz timer is running. Writing a 0 has no effect."]
157 #[inline(always)]
158 pub fn run(self) -> &'a mut crate::W<REG> {
159 self.variant(Wake1khz::Run)
160 }
161 #[doc = "Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit."]
162 #[inline(always)]
163 pub fn time_out(self) -> &'a mut crate::W<REG> {
164 self.variant(Wake1khz::TimeOut)
165 }
166}
167#[doc = "RTC 1 Hz timer alarm enable for Deep power-down.\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum AlarmdpdEn {
171 #[doc = "0: Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode."]
172 Disable = 0,
173 #[doc = "1: Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode."]
174 Enable = 1,
175}
176impl From<AlarmdpdEn> for bool {
177 #[inline(always)]
178 fn from(variant: AlarmdpdEn) -> Self {
179 variant as u8 != 0
180 }
181}
182#[doc = "Field `ALARMDPD_EN` reader - RTC 1 Hz timer alarm enable for Deep power-down."]
183pub type AlarmdpdEnR = crate::BitReader<AlarmdpdEn>;
184impl AlarmdpdEnR {
185 #[doc = "Get enumerated values variant"]
186 #[inline(always)]
187 pub const fn variant(&self) -> AlarmdpdEn {
188 match self.bits {
189 false => AlarmdpdEn::Disable,
190 true => AlarmdpdEn::Enable,
191 }
192 }
193 #[doc = "Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode."]
194 #[inline(always)]
195 pub fn is_disable(&self) -> bool {
196 *self == AlarmdpdEn::Disable
197 }
198 #[doc = "Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode."]
199 #[inline(always)]
200 pub fn is_enable(&self) -> bool {
201 *self == AlarmdpdEn::Enable
202 }
203}
204#[doc = "Field `ALARMDPD_EN` writer - RTC 1 Hz timer alarm enable for Deep power-down."]
205pub type AlarmdpdEnW<'a, REG> = crate::BitWriter<'a, REG, AlarmdpdEn>;
206impl<'a, REG> AlarmdpdEnW<'a, REG>
207where
208 REG: crate::Writable + crate::RegisterSpec,
209{
210 #[doc = "Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode."]
211 #[inline(always)]
212 pub fn disable(self) -> &'a mut crate::W<REG> {
213 self.variant(AlarmdpdEn::Disable)
214 }
215 #[doc = "Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode."]
216 #[inline(always)]
217 pub fn enable(self) -> &'a mut crate::W<REG> {
218 self.variant(AlarmdpdEn::Enable)
219 }
220}
221#[doc = "RTC 1 kHz timer wake-up enable for Deep power-down.\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum WakedpdEn {
225 #[doc = "0: Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode."]
226 Disable = 0,
227 #[doc = "1: Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode."]
228 Enable = 1,
229}
230impl From<WakedpdEn> for bool {
231 #[inline(always)]
232 fn from(variant: WakedpdEn) -> Self {
233 variant as u8 != 0
234 }
235}
236#[doc = "Field `WAKEDPD_EN` reader - RTC 1 kHz timer wake-up enable for Deep power-down."]
237pub type WakedpdEnR = crate::BitReader<WakedpdEn>;
238impl WakedpdEnR {
239 #[doc = "Get enumerated values variant"]
240 #[inline(always)]
241 pub const fn variant(&self) -> WakedpdEn {
242 match self.bits {
243 false => WakedpdEn::Disable,
244 true => WakedpdEn::Enable,
245 }
246 }
247 #[doc = "Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode."]
248 #[inline(always)]
249 pub fn is_disable(&self) -> bool {
250 *self == WakedpdEn::Disable
251 }
252 #[doc = "Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode."]
253 #[inline(always)]
254 pub fn is_enable(&self) -> bool {
255 *self == WakedpdEn::Enable
256 }
257}
258#[doc = "Field `WAKEDPD_EN` writer - RTC 1 kHz timer wake-up enable for Deep power-down."]
259pub type WakedpdEnW<'a, REG> = crate::BitWriter<'a, REG, WakedpdEn>;
260impl<'a, REG> WakedpdEnW<'a, REG>
261where
262 REG: crate::Writable + crate::RegisterSpec,
263{
264 #[doc = "Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode."]
265 #[inline(always)]
266 pub fn disable(self) -> &'a mut crate::W<REG> {
267 self.variant(WakedpdEn::Disable)
268 }
269 #[doc = "Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode."]
270 #[inline(always)]
271 pub fn enable(self) -> &'a mut crate::W<REG> {
272 self.variant(WakedpdEn::Enable)
273 }
274}
275#[doc = "RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0).\n\nValue on reset: 0"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum Rtc1khzEn {
279 #[doc = "0: Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode."]
280 Disable = 0,
281 #[doc = "1: Enable. The 1 kHz RTC timer is enabled."]
282 Enable = 1,
283}
284impl From<Rtc1khzEn> for bool {
285 #[inline(always)]
286 fn from(variant: Rtc1khzEn) -> Self {
287 variant as u8 != 0
288 }
289}
290#[doc = "Field `RTC1KHZ_EN` reader - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0)."]
291pub type Rtc1khzEnR = crate::BitReader<Rtc1khzEn>;
292impl Rtc1khzEnR {
293 #[doc = "Get enumerated values variant"]
294 #[inline(always)]
295 pub const fn variant(&self) -> Rtc1khzEn {
296 match self.bits {
297 false => Rtc1khzEn::Disable,
298 true => Rtc1khzEn::Enable,
299 }
300 }
301 #[doc = "Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode."]
302 #[inline(always)]
303 pub fn is_disable(&self) -> bool {
304 *self == Rtc1khzEn::Disable
305 }
306 #[doc = "Enable. The 1 kHz RTC timer is enabled."]
307 #[inline(always)]
308 pub fn is_enable(&self) -> bool {
309 *self == Rtc1khzEn::Enable
310 }
311}
312#[doc = "Field `RTC1KHZ_EN` writer - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0)."]
313pub type Rtc1khzEnW<'a, REG> = crate::BitWriter<'a, REG, Rtc1khzEn>;
314impl<'a, REG> Rtc1khzEnW<'a, REG>
315where
316 REG: crate::Writable + crate::RegisterSpec,
317{
318 #[doc = "Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode."]
319 #[inline(always)]
320 pub fn disable(self) -> &'a mut crate::W<REG> {
321 self.variant(Rtc1khzEn::Disable)
322 }
323 #[doc = "Enable. The 1 kHz RTC timer is enabled."]
324 #[inline(always)]
325 pub fn enable(self) -> &'a mut crate::W<REG> {
326 self.variant(Rtc1khzEn::Enable)
327 }
328}
329#[doc = "RTC enable.\n\nValue on reset: 0"]
330#[cfg_attr(feature = "defmt", derive(defmt::Format))]
331#[derive(Clone, Copy, Debug, PartialEq, Eq)]
332pub enum RtcEn {
333 #[doc = "0: Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register."]
334 Disable = 0,
335 #[doc = "1: Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register."]
336 Enable = 1,
337}
338impl From<RtcEn> for bool {
339 #[inline(always)]
340 fn from(variant: RtcEn) -> Self {
341 variant as u8 != 0
342 }
343}
344#[doc = "Field `RTC_EN` reader - RTC enable."]
345pub type RtcEnR = crate::BitReader<RtcEn>;
346impl RtcEnR {
347 #[doc = "Get enumerated values variant"]
348 #[inline(always)]
349 pub const fn variant(&self) -> RtcEn {
350 match self.bits {
351 false => RtcEn::Disable,
352 true => RtcEn::Enable,
353 }
354 }
355 #[doc = "Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register."]
356 #[inline(always)]
357 pub fn is_disable(&self) -> bool {
358 *self == RtcEn::Disable
359 }
360 #[doc = "Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register."]
361 #[inline(always)]
362 pub fn is_enable(&self) -> bool {
363 *self == RtcEn::Enable
364 }
365}
366#[doc = "Field `RTC_EN` writer - RTC enable."]
367pub type RtcEnW<'a, REG> = crate::BitWriter<'a, REG, RtcEn>;
368impl<'a, REG> RtcEnW<'a, REG>
369where
370 REG: crate::Writable + crate::RegisterSpec,
371{
372 #[doc = "Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register."]
373 #[inline(always)]
374 pub fn disable(self) -> &'a mut crate::W<REG> {
375 self.variant(RtcEn::Disable)
376 }
377 #[doc = "Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register."]
378 #[inline(always)]
379 pub fn enable(self) -> &'a mut crate::W<REG> {
380 self.variant(RtcEn::Enable)
381 }
382}
383#[doc = "The RTC oscillator enable\n\nValue on reset: 1"]
384#[cfg_attr(feature = "defmt", derive(defmt::Format))]
385#[derive(Clone, Copy, Debug, PartialEq, Eq)]
386pub enum RtcOscPd {
387 #[doc = "0: The RTC oscillator is enabled. This bit must be cleared in order for the RTC module to function"]
388 Enable = 0,
389 #[doc = "1: The RTC oscillator is shut-off to reserve power consumption. RTC operation is disabled."]
390 ShutOff = 1,
391}
392impl From<RtcOscPd> for bool {
393 #[inline(always)]
394 fn from(variant: RtcOscPd) -> Self {
395 variant as u8 != 0
396 }
397}
398#[doc = "Field `RTC_OSC_PD` reader - The RTC oscillator enable"]
399pub type RtcOscPdR = crate::BitReader<RtcOscPd>;
400impl RtcOscPdR {
401 #[doc = "Get enumerated values variant"]
402 #[inline(always)]
403 pub const fn variant(&self) -> RtcOscPd {
404 match self.bits {
405 false => RtcOscPd::Enable,
406 true => RtcOscPd::ShutOff,
407 }
408 }
409 #[doc = "The RTC oscillator is enabled. This bit must be cleared in order for the RTC module to function"]
410 #[inline(always)]
411 pub fn is_enable(&self) -> bool {
412 *self == RtcOscPd::Enable
413 }
414 #[doc = "The RTC oscillator is shut-off to reserve power consumption. RTC operation is disabled."]
415 #[inline(always)]
416 pub fn is_shut_off(&self) -> bool {
417 *self == RtcOscPd::ShutOff
418 }
419}
420#[doc = "Field `RTC_OSC_PD` writer - The RTC oscillator enable"]
421pub type RtcOscPdW<'a, REG> = crate::BitWriter<'a, REG, RtcOscPd>;
422impl<'a, REG> RtcOscPdW<'a, REG>
423where
424 REG: crate::Writable + crate::RegisterSpec,
425{
426 #[doc = "The RTC oscillator is enabled. This bit must be cleared in order for the RTC module to function"]
427 #[inline(always)]
428 pub fn enable(self) -> &'a mut crate::W<REG> {
429 self.variant(RtcOscPd::Enable)
430 }
431 #[doc = "The RTC oscillator is shut-off to reserve power consumption. RTC operation is disabled."]
432 #[inline(always)]
433 pub fn shut_off(self) -> &'a mut crate::W<REG> {
434 self.variant(RtcOscPd::ShutOff)
435 }
436}
437#[doc = "The 32 KHz sub-second counter enable\n\nValue on reset: 0"]
438#[cfg_attr(feature = "defmt", derive(defmt::Format))]
439#[derive(Clone, Copy, Debug, PartialEq, Eq)]
440pub enum RtcSubsecEna {
441 #[doc = "0: The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'"]
442 Disable = 0,
443 #[doc = "1: The 32 KHz sub-second counter is enabled (if implemented). Counting will commence on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) has been set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep_powerdown mode."]
444 Enable = 1,
445}
446impl From<RtcSubsecEna> for bool {
447 #[inline(always)]
448 fn from(variant: RtcSubsecEna) -> Self {
449 variant as u8 != 0
450 }
451}
452#[doc = "Field `RTC_SUBSEC_ENA` reader - The 32 KHz sub-second counter enable"]
453pub type RtcSubsecEnaR = crate::BitReader<RtcSubsecEna>;
454impl RtcSubsecEnaR {
455 #[doc = "Get enumerated values variant"]
456 #[inline(always)]
457 pub const fn variant(&self) -> RtcSubsecEna {
458 match self.bits {
459 false => RtcSubsecEna::Disable,
460 true => RtcSubsecEna::Enable,
461 }
462 }
463 #[doc = "The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'"]
464 #[inline(always)]
465 pub fn is_disable(&self) -> bool {
466 *self == RtcSubsecEna::Disable
467 }
468 #[doc = "The 32 KHz sub-second counter is enabled (if implemented). Counting will commence on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) has been set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep_powerdown mode."]
469 #[inline(always)]
470 pub fn is_enable(&self) -> bool {
471 *self == RtcSubsecEna::Enable
472 }
473}
474#[doc = "Field `RTC_SUBSEC_ENA` writer - The 32 KHz sub-second counter enable"]
475pub type RtcSubsecEnaW<'a, REG> = crate::BitWriter<'a, REG, RtcSubsecEna>;
476impl<'a, REG> RtcSubsecEnaW<'a, REG>
477where
478 REG: crate::Writable + crate::RegisterSpec,
479{
480 #[doc = "The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a '0'"]
481 #[inline(always)]
482 pub fn disable(self) -> &'a mut crate::W<REG> {
483 self.variant(RtcSubsecEna::Disable)
484 }
485 #[doc = "The 32 KHz sub-second counter is enabled (if implemented). Counting will commence on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) has been set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep_powerdown mode."]
486 #[inline(always)]
487 pub fn enable(self) -> &'a mut crate::W<REG> {
488 self.variant(RtcSubsecEna::Enable)
489 }
490}
491#[doc = "Field `RTC_OSC_loadcap` reader - capacitive load selection"]
492pub type RtcOscLoadcapR = crate::FieldReader;
493#[doc = "Field `RTC_OSC_loadcap` writer - capacitive load selection"]
494pub type RtcOscLoadcapW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
495impl R {
496 #[doc = "Bit 0 - Software reset control"]
497 #[inline(always)]
498 pub fn swreset(&self) -> SwresetR {
499 SwresetR::new((self.bits & 1) != 0)
500 }
501 #[doc = "Bit 2 - RTC 1 Hz timer alarm flag status."]
502 #[inline(always)]
503 pub fn alarm1hz(&self) -> Alarm1hzR {
504 Alarm1hzR::new(((self.bits >> 2) & 1) != 0)
505 }
506 #[doc = "Bit 3 - RTC 1 kHz timer wake-up flag status."]
507 #[inline(always)]
508 pub fn wake1khz(&self) -> Wake1khzR {
509 Wake1khzR::new(((self.bits >> 3) & 1) != 0)
510 }
511 #[doc = "Bit 4 - RTC 1 Hz timer alarm enable for Deep power-down."]
512 #[inline(always)]
513 pub fn alarmdpd_en(&self) -> AlarmdpdEnR {
514 AlarmdpdEnR::new(((self.bits >> 4) & 1) != 0)
515 }
516 #[doc = "Bit 5 - RTC 1 kHz timer wake-up enable for Deep power-down."]
517 #[inline(always)]
518 pub fn wakedpd_en(&self) -> WakedpdEnR {
519 WakedpdEnR::new(((self.bits >> 5) & 1) != 0)
520 }
521 #[doc = "Bit 6 - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0)."]
522 #[inline(always)]
523 pub fn rtc1khz_en(&self) -> Rtc1khzEnR {
524 Rtc1khzEnR::new(((self.bits >> 6) & 1) != 0)
525 }
526 #[doc = "Bit 7 - RTC enable."]
527 #[inline(always)]
528 pub fn rtc_en(&self) -> RtcEnR {
529 RtcEnR::new(((self.bits >> 7) & 1) != 0)
530 }
531 #[doc = "Bit 8 - The RTC oscillator enable"]
532 #[inline(always)]
533 pub fn rtc_osc_pd(&self) -> RtcOscPdR {
534 RtcOscPdR::new(((self.bits >> 8) & 1) != 0)
535 }
536 #[doc = "Bit 10 - The 32 KHz sub-second counter enable"]
537 #[inline(always)]
538 pub fn rtc_subsec_ena(&self) -> RtcSubsecEnaR {
539 RtcSubsecEnaR::new(((self.bits >> 10) & 1) != 0)
540 }
541 #[doc = "Bits 28:31 - capacitive load selection"]
542 #[inline(always)]
543 pub fn rtc_osc_loadcap(&self) -> RtcOscLoadcapR {
544 RtcOscLoadcapR::new(((self.bits >> 28) & 0x0f) as u8)
545 }
546}
547#[cfg(feature = "debug")]
548impl core::fmt::Debug for R {
549 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
550 f.debug_struct("CTRL")
551 .field("swreset", &self.swreset())
552 .field("alarm1hz", &self.alarm1hz())
553 .field("wake1khz", &self.wake1khz())
554 .field("alarmdpd_en", &self.alarmdpd_en())
555 .field("wakedpd_en", &self.wakedpd_en())
556 .field("rtc1khz_en", &self.rtc1khz_en())
557 .field("rtc_en", &self.rtc_en())
558 .field("rtc_osc_pd", &self.rtc_osc_pd())
559 .field("rtc_subsec_ena", &self.rtc_subsec_ena())
560 .field("rtc_osc_loadcap", &self.rtc_osc_loadcap())
561 .finish()
562 }
563}
564impl W {
565 #[doc = "Bit 0 - Software reset control"]
566 #[inline(always)]
567 pub fn swreset(&mut self) -> SwresetW<CtrlSpec> {
568 SwresetW::new(self, 0)
569 }
570 #[doc = "Bit 2 - RTC 1 Hz timer alarm flag status."]
571 #[inline(always)]
572 pub fn alarm1hz(&mut self) -> Alarm1hzW<CtrlSpec> {
573 Alarm1hzW::new(self, 2)
574 }
575 #[doc = "Bit 3 - RTC 1 kHz timer wake-up flag status."]
576 #[inline(always)]
577 pub fn wake1khz(&mut self) -> Wake1khzW<CtrlSpec> {
578 Wake1khzW::new(self, 3)
579 }
580 #[doc = "Bit 4 - RTC 1 Hz timer alarm enable for Deep power-down."]
581 #[inline(always)]
582 pub fn alarmdpd_en(&mut self) -> AlarmdpdEnW<CtrlSpec> {
583 AlarmdpdEnW::new(self, 4)
584 }
585 #[doc = "Bit 5 - RTC 1 kHz timer wake-up enable for Deep power-down."]
586 #[inline(always)]
587 pub fn wakedpd_en(&mut self) -> WakedpdEnW<CtrlSpec> {
588 WakedpdEnW::new(self, 5)
589 }
590 #[doc = "Bit 6 - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0)."]
591 #[inline(always)]
592 pub fn rtc1khz_en(&mut self) -> Rtc1khzEnW<CtrlSpec> {
593 Rtc1khzEnW::new(self, 6)
594 }
595 #[doc = "Bit 7 - RTC enable."]
596 #[inline(always)]
597 pub fn rtc_en(&mut self) -> RtcEnW<CtrlSpec> {
598 RtcEnW::new(self, 7)
599 }
600 #[doc = "Bit 8 - The RTC oscillator enable"]
601 #[inline(always)]
602 pub fn rtc_osc_pd(&mut self) -> RtcOscPdW<CtrlSpec> {
603 RtcOscPdW::new(self, 8)
604 }
605 #[doc = "Bit 10 - The 32 KHz sub-second counter enable"]
606 #[inline(always)]
607 pub fn rtc_subsec_ena(&mut self) -> RtcSubsecEnaW<CtrlSpec> {
608 RtcSubsecEnaW::new(self, 10)
609 }
610 #[doc = "Bits 28:31 - capacitive load selection"]
611 #[inline(always)]
612 pub fn rtc_osc_loadcap(&mut self) -> RtcOscLoadcapW<CtrlSpec> {
613 RtcOscLoadcapW::new(self, 28)
614 }
615}
616#[doc = "RTC control register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
617pub struct CtrlSpec;
618impl crate::RegisterSpec for CtrlSpec {
619 type Ux = u32;
620}
621#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
622impl crate::Readable for CtrlSpec {}
623#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
624impl crate::Writable for CtrlSpec {
625 type Safety = crate::Unsafe;
626 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
627 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
628}
629#[doc = "`reset()` method sets CTRL to value 0x1000_0103"]
630impl crate::Resettable for CtrlSpec {
631 const RESET_VALUE: u32 = 0x1000_0103;
632}