1#[repr(C)]
2#[cfg_attr(feature = "debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 _reserved0: [u8; 0x0800],
6 cfg: Cfg,
7 stat: Stat,
8 intenset: Intenset,
9 intenclr: Intenclr,
10 timeout: Timeout,
11 clkdiv: Clkdiv,
12 intstat: Intstat,
13 _reserved7: [u8; 0x04],
14 mstctl: Mstctl,
15 msttime: Msttime,
16 mstdat: Mstdat,
17 _reserved10: [u8; 0x14],
18 slvctl: Slvctl,
19 slvdat: Slvdat,
20 slvadr: [Slvadr; 4],
21 slvqual0: Slvqual0,
22 _reserved14: [u8; 0x24],
23 monrxdat: Monrxdat,
24 _reserved15: [u8; 0x0778],
25 id: Id,
26}
27impl RegisterBlock {
28 #[doc = "0x800 - Configuration for shared functions."]
29 #[inline(always)]
30 pub const fn cfg(&self) -> &Cfg {
31 &self.cfg
32 }
33 #[doc = "0x804 - Status register for Master, Slave, and Monitor functions."]
34 #[inline(always)]
35 pub const fn stat(&self) -> &Stat {
36 &self.stat
37 }
38 #[doc = "0x808 - Interrupt Enable Set and read register."]
39 #[inline(always)]
40 pub const fn intenset(&self) -> &Intenset {
41 &self.intenset
42 }
43 #[doc = "0x80c - Interrupt Enable Clear register."]
44 #[inline(always)]
45 pub const fn intenclr(&self) -> &Intenclr {
46 &self.intenclr
47 }
48 #[doc = "0x810 - Time-out value register."]
49 #[inline(always)]
50 pub const fn timeout(&self) -> &Timeout {
51 &self.timeout
52 }
53 #[doc = "0x814 - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function."]
54 #[inline(always)]
55 pub const fn clkdiv(&self) -> &Clkdiv {
56 &self.clkdiv
57 }
58 #[doc = "0x818 - Interrupt Status register for Master, Slave, and Monitor functions."]
59 #[inline(always)]
60 pub const fn intstat(&self) -> &Intstat {
61 &self.intstat
62 }
63 #[doc = "0x820 - Master control register."]
64 #[inline(always)]
65 pub const fn mstctl(&self) -> &Mstctl {
66 &self.mstctl
67 }
68 #[doc = "0x824 - Master timing configuration."]
69 #[inline(always)]
70 pub const fn msttime(&self) -> &Msttime {
71 &self.msttime
72 }
73 #[doc = "0x828 - Combined Master receiver and transmitter data register."]
74 #[inline(always)]
75 pub const fn mstdat(&self) -> &Mstdat {
76 &self.mstdat
77 }
78 #[doc = "0x840 - Slave control register."]
79 #[inline(always)]
80 pub const fn slvctl(&self) -> &Slvctl {
81 &self.slvctl
82 }
83 #[doc = "0x844 - Combined Slave receiver and transmitter data register."]
84 #[inline(always)]
85 pub const fn slvdat(&self) -> &Slvdat {
86 &self.slvdat
87 }
88 #[doc = "0x848..0x858 - Slave address register."]
89 #[inline(always)]
90 pub const fn slvadr(&self, n: usize) -> &Slvadr {
91 &self.slvadr[n]
92 }
93 #[doc = "Iterator for array of:"]
94 #[doc = "0x848..0x858 - Slave address register."]
95 #[inline(always)]
96 pub fn slvadr_iter(&self) -> impl Iterator<Item = &Slvadr> {
97 self.slvadr.iter()
98 }
99 #[doc = "0x858 - Slave Qualification for address 0."]
100 #[inline(always)]
101 pub const fn slvqual0(&self) -> &Slvqual0 {
102 &self.slvqual0
103 }
104 #[doc = "0x880 - Monitor receiver data register."]
105 #[inline(always)]
106 pub const fn monrxdat(&self) -> &Monrxdat {
107 &self.monrxdat
108 }
109 #[doc = "0xffc - Peripheral identification register."]
110 #[inline(always)]
111 pub const fn id(&self) -> &Id {
112 &self.id
113 }
114}
115#[doc = "CFG (rw) register accessor: Configuration for shared functions.\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg`]
116module"]
117#[doc(alias = "CFG")]
118pub type Cfg = crate::Reg<cfg::CfgSpec>;
119#[doc = "Configuration for shared functions."]
120pub mod cfg;
121#[doc = "STAT (rw) register accessor: Status register for Master, Slave, and Monitor functions.\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
122module"]
123#[doc(alias = "STAT")]
124pub type Stat = crate::Reg<stat::StatSpec>;
125#[doc = "Status register for Master, Slave, and Monitor functions."]
126pub mod stat;
127#[doc = "INTENSET (rw) register accessor: Interrupt Enable Set and read register.\n\nYou can [`read`](crate::Reg::read) this register and get [`intenset::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenset::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenset`]
128module"]
129#[doc(alias = "INTENSET")]
130pub type Intenset = crate::Reg<intenset::IntensetSpec>;
131#[doc = "Interrupt Enable Set and read register."]
132pub mod intenset;
133#[doc = "INTENCLR (w) register accessor: Interrupt Enable Clear register.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intenclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intenclr`]
134module"]
135#[doc(alias = "INTENCLR")]
136pub type Intenclr = crate::Reg<intenclr::IntenclrSpec>;
137#[doc = "Interrupt Enable Clear register."]
138pub mod intenclr;
139#[doc = "TIMEOUT (rw) register accessor: Time-out value register.\n\nYou can [`read`](crate::Reg::read) this register and get [`timeout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timeout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timeout`]
140module"]
141#[doc(alias = "TIMEOUT")]
142pub type Timeout = crate::Reg<timeout::TimeoutSpec>;
143#[doc = "Time-out value register."]
144pub mod timeout;
145#[doc = "CLKDIV (rw) register accessor: Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function.\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`]
146module"]
147#[doc(alias = "CLKDIV")]
148pub type Clkdiv = crate::Reg<clkdiv::ClkdivSpec>;
149#[doc = "Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function."]
150pub mod clkdiv;
151#[doc = "INTSTAT (r) register accessor: Interrupt Status register for Master, Slave, and Monitor functions.\n\nYou can [`read`](crate::Reg::read) this register and get [`intstat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intstat`]
152module"]
153#[doc(alias = "INTSTAT")]
154pub type Intstat = crate::Reg<intstat::IntstatSpec>;
155#[doc = "Interrupt Status register for Master, Slave, and Monitor functions."]
156pub mod intstat;
157#[doc = "MSTCTL (rw) register accessor: Master control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`mstctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mstctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mstctl`]
158module"]
159#[doc(alias = "MSTCTL")]
160pub type Mstctl = crate::Reg<mstctl::MstctlSpec>;
161#[doc = "Master control register."]
162pub mod mstctl;
163#[doc = "MSTTIME (rw) register accessor: Master timing configuration.\n\nYou can [`read`](crate::Reg::read) this register and get [`msttime::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msttime::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msttime`]
164module"]
165#[doc(alias = "MSTTIME")]
166pub type Msttime = crate::Reg<msttime::MsttimeSpec>;
167#[doc = "Master timing configuration."]
168pub mod msttime;
169#[doc = "MSTDAT (rw) register accessor: Combined Master receiver and transmitter data register.\n\nYou can [`read`](crate::Reg::read) this register and get [`mstdat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mstdat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mstdat`]
170module"]
171#[doc(alias = "MSTDAT")]
172pub type Mstdat = crate::Reg<mstdat::MstdatSpec>;
173#[doc = "Combined Master receiver and transmitter data register."]
174pub mod mstdat;
175#[doc = "SLVCTL (rw) register accessor: Slave control register.\n\nYou can [`read`](crate::Reg::read) this register and get [`slvctl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slvctl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slvctl`]
176module"]
177#[doc(alias = "SLVCTL")]
178pub type Slvctl = crate::Reg<slvctl::SlvctlSpec>;
179#[doc = "Slave control register."]
180pub mod slvctl;
181#[doc = "SLVDAT (rw) register accessor: Combined Slave receiver and transmitter data register.\n\nYou can [`read`](crate::Reg::read) this register and get [`slvdat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slvdat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slvdat`]
182module"]
183#[doc(alias = "SLVDAT")]
184pub type Slvdat = crate::Reg<slvdat::SlvdatSpec>;
185#[doc = "Combined Slave receiver and transmitter data register."]
186pub mod slvdat;
187#[doc = "SLVADR (rw) register accessor: Slave address register.\n\nYou can [`read`](crate::Reg::read) this register and get [`slvadr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slvadr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slvadr`]
188module"]
189#[doc(alias = "SLVADR")]
190pub type Slvadr = crate::Reg<slvadr::SlvadrSpec>;
191#[doc = "Slave address register."]
192pub mod slvadr;
193#[doc = "SLVQUAL0 (rw) register accessor: Slave Qualification for address 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`slvqual0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slvqual0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slvqual0`]
194module"]
195#[doc(alias = "SLVQUAL0")]
196pub type Slvqual0 = crate::Reg<slvqual0::Slvqual0Spec>;
197#[doc = "Slave Qualification for address 0."]
198pub mod slvqual0;
199#[doc = "MONRXDAT (r) register accessor: Monitor receiver data register.\n\nYou can [`read`](crate::Reg::read) this register and get [`monrxdat::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@monrxdat`]
200module"]
201#[doc(alias = "MONRXDAT")]
202pub type Monrxdat = crate::Reg<monrxdat::MonrxdatSpec>;
203#[doc = "Monitor receiver data register."]
204pub mod monrxdat;
205#[doc = "ID (r) register accessor: Peripheral identification register.\n\nYou can [`read`](crate::Reg::read) this register and get [`id::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id`]
206module"]
207#[doc(alias = "ID")]
208pub type Id = crate::Reg<id::IdSpec>;
209#[doc = "Peripheral identification register."]
210pub mod id;