mimxrt685s_pac/hashcrypt/
ctrl.rs1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available.\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Mode {
10 #[doc = "0: Disabled"]
11 Disabled = 0,
12 #[doc = "1: SHA1 is enabled"]
13 Sha1 = 1,
14 #[doc = "2: SHA2-256 is enabled"]
15 Sha2_256 = 2,
16 #[doc = "4: AES if available (see also CRYPTCFG register for more controls)"]
17 Aes = 4,
18 #[doc = "5: ICB-AES if available (see also CRYPTCFG register for more controls)"]
19 IcbAes = 5,
20}
21impl From<Mode> for u8 {
22 #[inline(always)]
23 fn from(variant: Mode) -> Self {
24 variant as _
25 }
26}
27impl crate::FieldSpec for Mode {
28 type Ux = u8;
29}
30impl crate::IsEnum for Mode {}
31#[doc = "Field `Mode` reader - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available."]
32pub type ModeR = crate::FieldReader<Mode>;
33impl ModeR {
34 #[doc = "Get enumerated values variant"]
35 #[inline(always)]
36 pub const fn variant(&self) -> Option<Mode> {
37 match self.bits {
38 0 => Some(Mode::Disabled),
39 1 => Some(Mode::Sha1),
40 2 => Some(Mode::Sha2_256),
41 4 => Some(Mode::Aes),
42 5 => Some(Mode::IcbAes),
43 _ => None,
44 }
45 }
46 #[doc = "Disabled"]
47 #[inline(always)]
48 pub fn is_disabled(&self) -> bool {
49 *self == Mode::Disabled
50 }
51 #[doc = "SHA1 is enabled"]
52 #[inline(always)]
53 pub fn is_sha1(&self) -> bool {
54 *self == Mode::Sha1
55 }
56 #[doc = "SHA2-256 is enabled"]
57 #[inline(always)]
58 pub fn is_sha2_256(&self) -> bool {
59 *self == Mode::Sha2_256
60 }
61 #[doc = "AES if available (see also CRYPTCFG register for more controls)"]
62 #[inline(always)]
63 pub fn is_aes(&self) -> bool {
64 *self == Mode::Aes
65 }
66 #[doc = "ICB-AES if available (see also CRYPTCFG register for more controls)"]
67 #[inline(always)]
68 pub fn is_icb_aes(&self) -> bool {
69 *self == Mode::IcbAes
70 }
71}
72#[doc = "Field `Mode` writer - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available."]
73pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mode>;
74impl<'a, REG> ModeW<'a, REG>
75where
76 REG: crate::Writable + crate::RegisterSpec,
77 REG::Ux: From<u8>,
78{
79 #[doc = "Disabled"]
80 #[inline(always)]
81 pub fn disabled(self) -> &'a mut crate::W<REG> {
82 self.variant(Mode::Disabled)
83 }
84 #[doc = "SHA1 is enabled"]
85 #[inline(always)]
86 pub fn sha1(self) -> &'a mut crate::W<REG> {
87 self.variant(Mode::Sha1)
88 }
89 #[doc = "SHA2-256 is enabled"]
90 #[inline(always)]
91 pub fn sha2_256(self) -> &'a mut crate::W<REG> {
92 self.variant(Mode::Sha2_256)
93 }
94 #[doc = "AES if available (see also CRYPTCFG register for more controls)"]
95 #[inline(always)]
96 pub fn aes(self) -> &'a mut crate::W<REG> {
97 self.variant(Mode::Aes)
98 }
99 #[doc = "ICB-AES if available (see also CRYPTCFG register for more controls)"]
100 #[inline(always)]
101 pub fn icb_aes(self) -> &'a mut crate::W<REG> {
102 self.variant(Mode::IcbAes)
103 }
104}
105#[doc = "Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1.\n\nValue on reset: 0"]
106#[cfg_attr(feature = "defmt", derive(defmt::Format))]
107#[derive(Clone, Copy, Debug, PartialEq, Eq)]
108pub enum NewHash {
109 #[doc = "1: Starts a new Hash/Crypto and initializes the Digest/Result."]
110 Start = 1,
111}
112impl From<NewHash> for bool {
113 #[inline(always)]
114 fn from(variant: NewHash) -> Self {
115 variant as u8 != 0
116 }
117}
118#[doc = "Field `New_Hash` writer - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1."]
119pub type NewHashW<'a, REG> = crate::BitWriter<'a, REG, NewHash>;
120impl<'a, REG> NewHashW<'a, REG>
121where
122 REG: crate::Writable + crate::RegisterSpec,
123{
124 #[doc = "Starts a new Hash/Crypto and initializes the Digest/Result."]
125 #[inline(always)]
126 pub fn start(self) -> &'a mut crate::W<REG> {
127 self.variant(NewHash::Start)
128 }
129}
130#[doc = "If 1, allows the SHA RELOAD registers to be used. This is used to save a partial Hash Digest (e.g. when need to run AES) and then reload it later for continuation.\n\nValue on reset: 0"]
131#[cfg_attr(feature = "defmt", derive(defmt::Format))]
132#[derive(Clone, Copy, Debug, PartialEq, Eq)]
133pub enum Reload {
134 #[doc = "1: Allow RELOAD registers to be used."]
135 Reload = 1,
136}
137impl From<Reload> for bool {
138 #[inline(always)]
139 fn from(variant: Reload) -> Self {
140 variant as u8 != 0
141 }
142}
143#[doc = "Field `RELOAD` reader - If 1, allows the SHA RELOAD registers to be used. This is used to save a partial Hash Digest (e.g. when need to run AES) and then reload it later for continuation."]
144pub type ReloadR = crate::BitReader<Reload>;
145impl ReloadR {
146 #[doc = "Get enumerated values variant"]
147 #[inline(always)]
148 pub const fn variant(&self) -> Option<Reload> {
149 match self.bits {
150 true => Some(Reload::Reload),
151 _ => None,
152 }
153 }
154 #[doc = "Allow RELOAD registers to be used."]
155 #[inline(always)]
156 pub fn is_reload(&self) -> bool {
157 *self == Reload::Reload
158 }
159}
160#[doc = "Field `RELOAD` writer - If 1, allows the SHA RELOAD registers to be used. This is used to save a partial Hash Digest (e.g. when need to run AES) and then reload it later for continuation."]
161pub type ReloadW<'a, REG> = crate::BitWriter<'a, REG, Reload>;
162impl<'a, REG> ReloadW<'a, REG>
163where
164 REG: crate::Writable + crate::RegisterSpec,
165{
166 #[doc = "Allow RELOAD registers to be used."]
167 #[inline(always)]
168 pub fn reload(self) -> &'a mut crate::W<REG> {
169 self.variant(Reload::Reload)
170 }
171}
172#[doc = "Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed).\n\nValue on reset: 0"]
173#[cfg_attr(feature = "defmt", derive(defmt::Format))]
174#[derive(Clone, Copy, Debug, PartialEq, Eq)]
175pub enum DmaI {
176 #[doc = "0: DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used."]
177 NotUsed = 0,
178 #[doc = "1: DMA will push in the data."]
179 Push = 1,
180}
181impl From<DmaI> for bool {
182 #[inline(always)]
183 fn from(variant: DmaI) -> Self {
184 variant as u8 != 0
185 }
186}
187#[doc = "Field `DMA_I` reader - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed)."]
188pub type DmaIR = crate::BitReader<DmaI>;
189impl DmaIR {
190 #[doc = "Get enumerated values variant"]
191 #[inline(always)]
192 pub const fn variant(&self) -> DmaI {
193 match self.bits {
194 false => DmaI::NotUsed,
195 true => DmaI::Push,
196 }
197 }
198 #[doc = "DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used."]
199 #[inline(always)]
200 pub fn is_not_used(&self) -> bool {
201 *self == DmaI::NotUsed
202 }
203 #[doc = "DMA will push in the data."]
204 #[inline(always)]
205 pub fn is_push(&self) -> bool {
206 *self == DmaI::Push
207 }
208}
209#[doc = "Field `DMA_I` writer - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed)."]
210pub type DmaIW<'a, REG> = crate::BitWriter<'a, REG, DmaI>;
211impl<'a, REG> DmaIW<'a, REG>
212where
213 REG: crate::Writable + crate::RegisterSpec,
214{
215 #[doc = "DMA is not used. Processor writes the necessary words when WAITING is set (interrupts), unless AHB Master is used."]
216 #[inline(always)]
217 pub fn not_used(self) -> &'a mut crate::W<REG> {
218 self.variant(DmaI::NotUsed)
219 }
220 #[doc = "DMA will push in the data."]
221 #[inline(always)]
222 pub fn push(self) -> &'a mut crate::W<REG> {
223 self.variant(DmaI::Push)
224 }
225}
226#[doc = "Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses.\n\nValue on reset: 0"]
227#[cfg_attr(feature = "defmt", derive(defmt::Format))]
228#[derive(Clone, Copy, Debug, PartialEq, Eq)]
229pub enum DmaO {
230 #[doc = "0: DMA is not used. Processor reads the digest/output in response to DIGEST interrupt."]
231 Notused = 0,
232}
233impl From<DmaO> for bool {
234 #[inline(always)]
235 fn from(variant: DmaO) -> Self {
236 variant as u8 != 0
237 }
238}
239#[doc = "Field `DMA_O` reader - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses."]
240pub type DmaOR = crate::BitReader<DmaO>;
241impl DmaOR {
242 #[doc = "Get enumerated values variant"]
243 #[inline(always)]
244 pub const fn variant(&self) -> Option<DmaO> {
245 match self.bits {
246 false => Some(DmaO::Notused),
247 _ => None,
248 }
249 }
250 #[doc = "DMA is not used. Processor reads the digest/output in response to DIGEST interrupt."]
251 #[inline(always)]
252 pub fn is_notused(&self) -> bool {
253 *self == DmaO::Notused
254 }
255}
256#[doc = "Field `DMA_O` writer - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses."]
257pub type DmaOW<'a, REG> = crate::BitWriter<'a, REG, DmaO>;
258impl<'a, REG> DmaOW<'a, REG>
259where
260 REG: crate::Writable + crate::RegisterSpec,
261{
262 #[doc = "DMA is not used. Processor reads the digest/output in response to DIGEST interrupt."]
263 #[inline(always)]
264 pub fn notused(self) -> &'a mut crate::W<REG> {
265 self.variant(DmaO::Notused)
266 }
267}
268#[doc = "Field `HASHSWPB` reader - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register."]
269pub type HashswpbR = crate::BitReader;
270#[doc = "Field `HASHSWPB` writer - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register."]
271pub type HashswpbW<'a, REG> = crate::BitWriter<'a, REG>;
272impl R {
273 #[doc = "Bits 0:2 - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available."]
274 #[inline(always)]
275 pub fn mode(&self) -> ModeR {
276 ModeR::new((self.bits & 7) as u8)
277 }
278 #[doc = "Bit 5 - If 1, allows the SHA RELOAD registers to be used. This is used to save a partial Hash Digest (e.g. when need to run AES) and then reload it later for continuation."]
279 #[inline(always)]
280 pub fn reload(&self) -> ReloadR {
281 ReloadR::new(((self.bits >> 5) & 1) != 0)
282 }
283 #[doc = "Bit 8 - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed)."]
284 #[inline(always)]
285 pub fn dma_i(&self) -> DmaIR {
286 DmaIR::new(((self.bits >> 8) & 1) != 0)
287 }
288 #[doc = "Bit 9 - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses."]
289 #[inline(always)]
290 pub fn dma_o(&self) -> DmaOR {
291 DmaOR::new(((self.bits >> 9) & 1) != 0)
292 }
293 #[doc = "Bit 12 - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register."]
294 #[inline(always)]
295 pub fn hashswpb(&self) -> HashswpbR {
296 HashswpbR::new(((self.bits >> 12) & 1) != 0)
297 }
298}
299#[cfg(feature = "debug")]
300impl core::fmt::Debug for R {
301 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
302 f.debug_struct("CTRL")
303 .field("mode", &self.mode())
304 .field("reload", &self.reload())
305 .field("dma_i", &self.dma_i())
306 .field("dma_o", &self.dma_o())
307 .field("hashswpb", &self.hashswpb())
308 .finish()
309 }
310}
311impl W {
312 #[doc = "Bits 0:2 - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if specific modes beyond SHA1 and SHA2-256 are available."]
313 #[inline(always)]
314 pub fn mode(&mut self) -> ModeW<CtrlSpec> {
315 ModeW::new(self, 0)
316 }
317 #[doc = "Bit 4 - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1."]
318 #[inline(always)]
319 pub fn new_hash(&mut self) -> NewHashW<CtrlSpec> {
320 NewHashW::new(self, 4)
321 }
322 #[doc = "Bit 5 - If 1, allows the SHA RELOAD registers to be used. This is used to save a partial Hash Digest (e.g. when need to run AES) and then reload it later for continuation."]
323 #[inline(always)]
324 pub fn reload(&mut self) -> ReloadW<CtrlSpec> {
325 ReloadW::new(self, 5)
326 }
327 #[doc = "Bit 8 - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words and then will process the Hash. If Cryptographic, it will load as many words as needed, including key if not already loaded. It will then request again. Normal model is that the DMA interrupts the processor when its length expires. Note that if the processor will write the key and optionally IV, it should not enable this until it has done so. Otherwise, the DMA will be expected to load those for the 1st block (when needed)."]
328 #[inline(always)]
329 pub fn dma_i(&mut self) -> DmaIW<CtrlSpec> {
330 DmaIW::new(self, 8)
331 }
332 #[doc = "Bit 9 - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the DMA has to know to switch direction and the locations. This can be used for crypto uses."]
333 #[inline(always)]
334 pub fn dma_o(&mut self) -> DmaOW<CtrlSpec> {
335 DmaOW::new(self, 9)
336 }
337 #[doc = "Bit 12 - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For cryptographic swapping, see the CRYPTCFG register."]
338 #[inline(always)]
339 pub fn hashswpb(&mut self) -> HashswpbW<CtrlSpec> {
340 HashswpbW::new(self, 12)
341 }
342}
343#[doc = "Control register to enable and operate Hash and Crypto\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
344pub struct CtrlSpec;
345impl crate::RegisterSpec for CtrlSpec {
346 type Ux = u32;
347}
348#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
349impl crate::Readable for CtrlSpec {}
350#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
351impl crate::Writable for CtrlSpec {
352 type Safety = crate::Unsafe;
353 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
354 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
355}
356#[doc = "`reset()` method sets CTRL to value 0"]
357impl crate::Resettable for CtrlSpec {
358 const RESET_VALUE: u32 = 0;
359}