mimxrt685s_pac/gpio/
clr.rs

1#[doc = "Register `CLR[%s]` writer"]
2pub type W = crate::W<ClrSpec>;
3#[doc = "Field `CLRP` writer - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."]
4pub type ClrpW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
5#[cfg(feature = "debug")]
6impl core::fmt::Debug for crate::generic::Reg<ClrSpec> {
7    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
8        write!(f, "(not readable)")
9    }
10}
11impl W {
12    #[doc = "Bits 0:31 - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit."]
13    #[inline(always)]
14    pub fn clrp(&mut self) -> ClrpW<ClrSpec> {
15        ClrpW::new(self, 0)
16    }
17}
18#[doc = "Clear port\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19pub struct ClrSpec;
20impl crate::RegisterSpec for ClrSpec {
21    type Ux = u32;
22}
23#[doc = "`write(|w| ..)` method takes [`clr::W`](W) writer structure"]
24impl crate::Writable for ClrSpec {
25    type Safety = crate::Unsafe;
26    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
27    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
28}
29#[doc = "`reset()` method sets CLR[%s]
30to value 0"]
31impl crate::Resettable for ClrSpec {
32    const RESET_VALUE: u32 = 0;
33}
mimxrt685s_pac/gpio/clr.rs

mimxrt685s_pac/gpio/
clr.rs
