mimxrt685s_pac/flexspi/
ahbrxbuf4cr0.rs

1#[doc = "Register `AHBRXBUF4CR0` reader"]
2pub type R = crate::R<Ahbrxbuf4cr0Spec>;
3#[doc = "Register `AHBRXBUF4CR0` writer"]
4pub type W = crate::W<Ahbrxbuf4cr0Spec>;
5#[doc = "Field `BUFSZ` reader - AHB RX Buffer Size in 64 bits."]
6pub type BufszR = crate::FieldReader<u16>;
7#[doc = "Field `BUFSZ` writer - AHB RX Buffer Size in 64 bits."]
8pub type BufszW<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
9#[doc = "Field `MSTRID` reader - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."]
10pub type MstridR = crate::FieldReader;
11#[doc = "Field `MSTRID` writer - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."]
12pub type MstridW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `PRIORITY` reader - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest."]
14pub type PriorityR = crate::FieldReader;
15#[doc = "Field `PRIORITY` writer - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest."]
16pub type PriorityW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `PREFETCHEN` reader - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master."]
18pub type PrefetchenR = crate::BitReader;
19#[doc = "Field `PREFETCHEN` writer - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master."]
20pub type PrefetchenW<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bits 0:8 - AHB RX Buffer Size in 64 bits."]
23    #[inline(always)]
24    pub fn bufsz(&self) -> BufszR {
25        BufszR::new((self.bits & 0x01ff) as u16)
26    }
27    #[doc = "Bits 16:19 - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."]
28    #[inline(always)]
29    pub fn mstrid(&self) -> MstridR {
30        MstridR::new(((self.bits >> 16) & 0x0f) as u8)
31    }
32    #[doc = "Bits 24:26 - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest."]
33    #[inline(always)]
34    pub fn priority(&self) -> PriorityR {
35        PriorityR::new(((self.bits >> 24) & 7) as u8)
36    }
37    #[doc = "Bit 31 - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master."]
38    #[inline(always)]
39    pub fn prefetchen(&self) -> PrefetchenR {
40        PrefetchenR::new(((self.bits >> 31) & 1) != 0)
41    }
42}
43#[cfg(feature = "debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("AHBRXBUF4CR0")
47            .field("bufsz", &self.bufsz())
48            .field("mstrid", &self.mstrid())
49            .field("priority", &self.priority())
50            .field("prefetchen", &self.prefetchen())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:8 - AHB RX Buffer Size in 64 bits."]
56    #[inline(always)]
57    pub fn bufsz(&mut self) -> BufszW<Ahbrxbuf4cr0Spec> {
58        BufszW::new(self, 0)
59    }
60    #[doc = "Bits 16:19 - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID)."]
61    #[inline(always)]
62    pub fn mstrid(&mut self) -> MstridW<Ahbrxbuf4cr0Spec> {
63        MstridW::new(self, 16)
64    }
65    #[doc = "Bits 24:26 - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest."]
66    #[inline(always)]
67    pub fn priority(&mut self) -> PriorityW<Ahbrxbuf4cr0Spec> {
68        PriorityW::new(self, 24)
69    }
70    #[doc = "Bit 31 - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master."]
71    #[inline(always)]
72    pub fn prefetchen(&mut self) -> PrefetchenW<Ahbrxbuf4cr0Spec> {
73        PrefetchenW::new(self, 31)
74    }
75}
76#[doc = "AHB RX Buffer 4 Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ahbrxbuf4cr0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahbrxbuf4cr0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct Ahbrxbuf4cr0Spec;
78impl crate::RegisterSpec for Ahbrxbuf4cr0Spec {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`ahbrxbuf4cr0::R`](R) reader structure"]
82impl crate::Readable for Ahbrxbuf4cr0Spec {}
83#[doc = "`write(|w| ..)` method takes [`ahbrxbuf4cr0::W`](W) writer structure"]
84impl crate::Writable for Ahbrxbuf4cr0Spec {
85    type Safety = crate::Unsafe;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets AHBRXBUF4CR0 to value 0x8004_0020"]
90impl crate::Resettable for Ahbrxbuf4cr0Spec {
91    const RESET_VALUE: u32 = 0x8004_0020;
92}
mimxrt685s_pac/flexspi/ahbrxbuf4cr0.rs

mimxrt685s_pac/flexspi/
ahbrxbuf4cr0.rs
