mimxrt685s_pac/clkctl1/
audiopll0ctl0.rs

1#[doc = "Register `AUDIOPLL0CTL0` reader"]
2pub type R = crate::R<Audiopll0ctl0Spec>;
3#[doc = "Register `AUDIOPLL0CTL0` writer"]
4pub type W = crate::W<Audiopll0ctl0Spec>;
5#[doc = "AUDIOPLL0 BYPASS Mode\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Bypass {
9    #[doc = "0: PFD output is PFD programmed clock."]
10    ProgrammedClk = 0,
11    #[doc = "1: PFD output is AUDIOPLL0 reference input clock. (Bypass Mode)"]
12    Bypass = 1,
13}
14impl From<Bypass> for bool {
15    #[inline(always)]
16    fn from(variant: Bypass) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `BYPASS` reader - AUDIOPLL0 BYPASS Mode"]
21pub type BypassR = crate::BitReader<Bypass>;
22impl BypassR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Bypass {
26        match self.bits {
27            false => Bypass::ProgrammedClk,
28            true => Bypass::Bypass,
29        }
30    }
31    #[doc = "PFD output is PFD programmed clock."]
32    #[inline(always)]
33    pub fn is_programmed_clk(&self) -> bool {
34        *self == Bypass::ProgrammedClk
35    }
36    #[doc = "PFD output is AUDIOPLL0 reference input clock. (Bypass Mode)"]
37    #[inline(always)]
38    pub fn is_bypass(&self) -> bool {
39        *self == Bypass::Bypass
40    }
41}
42#[doc = "Field `BYPASS` writer - AUDIOPLL0 BYPASS Mode"]
43pub type BypassW<'a, REG> = crate::BitWriter<'a, REG, Bypass>;
44impl<'a, REG> BypassW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "PFD output is PFD programmed clock."]
49    #[inline(always)]
50    pub fn programmed_clk(self) -> &'a mut crate::W<REG> {
51        self.variant(Bypass::ProgrammedClk)
52    }
53    #[doc = "PFD output is AUDIOPLL0 reference input clock. (Bypass Mode)"]
54    #[inline(always)]
55    pub fn bypass(self) -> &'a mut crate::W<REG> {
56        self.variant(Bypass::Bypass)
57    }
58}
59#[doc = "AUDIOPLL0 Reset:\n\nValue on reset: 1"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Reset {
63    #[doc = "0: AUDIOPLL0 reset is removed."]
64    Normal = 0,
65    #[doc = "1: AUDIOPLL0 is placed into reset."]
66    Reset = 1,
67}
68impl From<Reset> for bool {
69    #[inline(always)]
70    fn from(variant: Reset) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `RESET` reader - AUDIOPLL0 Reset:"]
75pub type ResetR = crate::BitReader<Reset>;
76impl ResetR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Reset {
80        match self.bits {
81            false => Reset::Normal,
82            true => Reset::Reset,
83        }
84    }
85    #[doc = "AUDIOPLL0 reset is removed."]
86    #[inline(always)]
87    pub fn is_normal(&self) -> bool {
88        *self == Reset::Normal
89    }
90    #[doc = "AUDIOPLL0 is placed into reset."]
91    #[inline(always)]
92    pub fn is_reset(&self) -> bool {
93        *self == Reset::Reset
94    }
95}
96#[doc = "Field `RESET` writer - AUDIOPLL0 Reset:"]
97pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>;
98impl<'a, REG> ResetW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "AUDIOPLL0 reset is removed."]
103    #[inline(always)]
104    pub fn normal(self) -> &'a mut crate::W<REG> {
105        self.variant(Reset::Normal)
106    }
107    #[doc = "AUDIOPLL0 is placed into reset."]
108    #[inline(always)]
109    pub fn reset(self) -> &'a mut crate::W<REG> {
110        self.variant(Reset::Reset)
111    }
112}
113#[doc = "Hold Ring Off Control\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum HoldringoffEna {
117    #[doc = "0: disbale"]
118    Dsiable = 0,
119    #[doc = "1: enable"]
120    Enable = 1,
121}
122impl From<HoldringoffEna> for bool {
123    #[inline(always)]
124    fn from(variant: HoldringoffEna) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `HOLDRINGOFF_ENA` reader - Hold Ring Off Control"]
129pub type HoldringoffEnaR = crate::BitReader<HoldringoffEna>;
130impl HoldringoffEnaR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> HoldringoffEna {
134        match self.bits {
135            false => HoldringoffEna::Dsiable,
136            true => HoldringoffEna::Enable,
137        }
138    }
139    #[doc = "disbale"]
140    #[inline(always)]
141    pub fn is_dsiable(&self) -> bool {
142        *self == HoldringoffEna::Dsiable
143    }
144    #[doc = "enable"]
145    #[inline(always)]
146    pub fn is_enable(&self) -> bool {
147        *self == HoldringoffEna::Enable
148    }
149}
150#[doc = "Field `HOLDRINGOFF_ENA` writer - Hold Ring Off Control"]
151pub type HoldringoffEnaW<'a, REG> = crate::BitWriter<'a, REG, HoldringoffEna>;
152impl<'a, REG> HoldringoffEnaW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "disbale"]
157    #[inline(always)]
158    pub fn dsiable(self) -> &'a mut crate::W<REG> {
159        self.variant(HoldringoffEna::Dsiable)
160    }
161    #[doc = "enable"]
162    #[inline(always)]
163    pub fn enable(self) -> &'a mut crate::W<REG> {
164        self.variant(HoldringoffEna::Enable)
165    }
166}
167#[doc = "Multiplication Factor for FAUDIOPLL0_OUTPUT:\n\nValue on reset: 22"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170#[repr(u8)]
171pub enum Mult {
172    #[doc = "16: Div 16"]
173    Div16 = 16,
174    #[doc = "17: Div 17"]
175    Div17 = 17,
176    #[doc = "20: Div 20"]
177    Div20 = 20,
178    #[doc = "22: Div 22"]
179    Div22 = 22,
180    #[doc = "27: Div 27"]
181    Div27 = 27,
182    #[doc = "33: Div 33"]
183    Div33 = 33,
184}
185impl From<Mult> for u8 {
186    #[inline(always)]
187    fn from(variant: Mult) -> Self {
188        variant as _
189    }
190}
191impl crate::FieldSpec for Mult {
192    type Ux = u8;
193}
194impl crate::IsEnum for Mult {}
195#[doc = "Field `MULT` reader - Multiplication Factor for FAUDIOPLL0_OUTPUT:"]
196pub type MultR = crate::FieldReader<Mult>;
197impl MultR {
198    #[doc = "Get enumerated values variant"]
199    #[inline(always)]
200    pub const fn variant(&self) -> Option<Mult> {
201        match self.bits {
202            16 => Some(Mult::Div16),
203            17 => Some(Mult::Div17),
204            20 => Some(Mult::Div20),
205            22 => Some(Mult::Div22),
206            27 => Some(Mult::Div27),
207            33 => Some(Mult::Div33),
208            _ => None,
209        }
210    }
211    #[doc = "Div 16"]
212    #[inline(always)]
213    pub fn is_div_16(&self) -> bool {
214        *self == Mult::Div16
215    }
216    #[doc = "Div 17"]
217    #[inline(always)]
218    pub fn is_div_17(&self) -> bool {
219        *self == Mult::Div17
220    }
221    #[doc = "Div 20"]
222    #[inline(always)]
223    pub fn is_div_20(&self) -> bool {
224        *self == Mult::Div20
225    }
226    #[doc = "Div 22"]
227    #[inline(always)]
228    pub fn is_div_22(&self) -> bool {
229        *self == Mult::Div22
230    }
231    #[doc = "Div 27"]
232    #[inline(always)]
233    pub fn is_div_27(&self) -> bool {
234        *self == Mult::Div27
235    }
236    #[doc = "Div 33"]
237    #[inline(always)]
238    pub fn is_div_33(&self) -> bool {
239        *self == Mult::Div33
240    }
241}
242#[doc = "Field `MULT` writer - Multiplication Factor for FAUDIOPLL0_OUTPUT:"]
243pub type MultW<'a, REG> = crate::FieldWriter<'a, REG, 8, Mult>;
244impl<'a, REG> MultW<'a, REG>
245where
246    REG: crate::Writable + crate::RegisterSpec,
247    REG::Ux: From<u8>,
248{
249    #[doc = "Div 16"]
250    #[inline(always)]
251    pub fn div_16(self) -> &'a mut crate::W<REG> {
252        self.variant(Mult::Div16)
253    }
254    #[doc = "Div 17"]
255    #[inline(always)]
256    pub fn div_17(self) -> &'a mut crate::W<REG> {
257        self.variant(Mult::Div17)
258    }
259    #[doc = "Div 20"]
260    #[inline(always)]
261    pub fn div_20(self) -> &'a mut crate::W<REG> {
262        self.variant(Mult::Div20)
263    }
264    #[doc = "Div 22"]
265    #[inline(always)]
266    pub fn div_22(self) -> &'a mut crate::W<REG> {
267        self.variant(Mult::Div22)
268    }
269    #[doc = "Div 27"]
270    #[inline(always)]
271    pub fn div_27(self) -> &'a mut crate::W<REG> {
272        self.variant(Mult::Div27)
273    }
274    #[doc = "Div 33"]
275    #[inline(always)]
276    pub fn div_33(self) -> &'a mut crate::W<REG> {
277        self.variant(Mult::Div33)
278    }
279}
280impl R {
281    #[doc = "Bit 0 - AUDIOPLL0 BYPASS Mode"]
282    #[inline(always)]
283    pub fn bypass(&self) -> BypassR {
284        BypassR::new((self.bits & 1) != 0)
285    }
286    #[doc = "Bit 1 - AUDIOPLL0 Reset:"]
287    #[inline(always)]
288    pub fn reset(&self) -> ResetR {
289        ResetR::new(((self.bits >> 1) & 1) != 0)
290    }
291    #[doc = "Bit 13 - Hold Ring Off Control"]
292    #[inline(always)]
293    pub fn holdringoff_ena(&self) -> HoldringoffEnaR {
294        HoldringoffEnaR::new(((self.bits >> 13) & 1) != 0)
295    }
296    #[doc = "Bits 16:23 - Multiplication Factor for FAUDIOPLL0_OUTPUT:"]
297    #[inline(always)]
298    pub fn mult(&self) -> MultR {
299        MultR::new(((self.bits >> 16) & 0xff) as u8)
300    }
301}
302#[cfg(feature = "debug")]
303impl core::fmt::Debug for R {
304    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
305        f.debug_struct("AUDIOPLL0CTL0")
306            .field("bypass", &self.bypass())
307            .field("reset", &self.reset())
308            .field("holdringoff_ena", &self.holdringoff_ena())
309            .field("mult", &self.mult())
310            .finish()
311    }
312}
313impl W {
314    #[doc = "Bit 0 - AUDIOPLL0 BYPASS Mode"]
315    #[inline(always)]
316    pub fn bypass(&mut self) -> BypassW<Audiopll0ctl0Spec> {
317        BypassW::new(self, 0)
318    }
319    #[doc = "Bit 1 - AUDIOPLL0 Reset:"]
320    #[inline(always)]
321    pub fn reset(&mut self) -> ResetW<Audiopll0ctl0Spec> {
322        ResetW::new(self, 1)
323    }
324    #[doc = "Bit 13 - Hold Ring Off Control"]
325    #[inline(always)]
326    pub fn holdringoff_ena(&mut self) -> HoldringoffEnaW<Audiopll0ctl0Spec> {
327        HoldringoffEnaW::new(self, 13)
328    }
329    #[doc = "Bits 16:23 - Multiplication Factor for FAUDIOPLL0_OUTPUT:"]
330    #[inline(always)]
331    pub fn mult(&mut self) -> MultW<Audiopll0ctl0Spec> {
332        MultW::new(self, 16)
333    }
334}
335#[doc = "audio pll0 control0\n\nYou can [`read`](crate::Reg::read) this register and get [`audiopll0ctl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`audiopll0ctl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
336pub struct Audiopll0ctl0Spec;
337impl crate::RegisterSpec for Audiopll0ctl0Spec {
338    type Ux = u32;
339}
340#[doc = "`read()` method returns [`audiopll0ctl0::R`](R) reader structure"]
341impl crate::Readable for Audiopll0ctl0Spec {}
342#[doc = "`write(|w| ..)` method takes [`audiopll0ctl0::W`](W) writer structure"]
343impl crate::Writable for Audiopll0ctl0Spec {
344    type Safety = crate::Unsafe;
345    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
346    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
347}
348#[doc = "`reset()` method sets AUDIOPLL0CTL0 to value 0x0016_0002"]
349impl crate::Resettable for Audiopll0ctl0Spec {
350    const RESET_VALUE: u32 = 0x0016_0002;
351}
mimxrt685s_pac/clkctl1/audiopll0ctl0.rs

mimxrt685s_pac/clkctl1/
audiopll0ctl0.rs
