mimxrt685s_pac/clkctl0/
flexspifclkdiv.rs

1#[doc = "Register `FLEXSPIFCLKDIV` reader"]
2pub type R = crate::R<FlexspifclkdivSpec>;
3#[doc = "Register `FLEXSPIFCLKDIV` writer"]
4pub type W = crate::W<FlexspifclkdivSpec>;
5#[doc = "Field `DIV` reader - Clock Divider Value Selection. . . 0: Divide by 1. ... 255: Divide by 256."]
6pub type DivR = crate::FieldReader;
7#[doc = "Field `DIV` writer - Clock Divider Value Selection. . . 0: Divide by 1. ... 255: Divide by 256."]
8pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `RESET` reader - Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count."]
10pub type ResetR = crate::BitReader;
11#[doc = "Field `RESET` writer - Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count."]
12pub type ResetW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `HALT` reader - Halts the divider counter. The intent is to allow the divider's clock source to be changed without the risk of a glitch at the output."]
14pub type HaltR = crate::BitReader;
15#[doc = "Field `HALT` writer - Halts the divider counter. The intent is to allow the divider's clock source to be changed without the risk of a glitch at the output."]
16pub type HaltW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `REQFLAG` reader - Divider status flag. Set when a change is made to the divider value, cleared when the change is complete."]
18pub type ReqflagR = crate::BitReader;
19#[doc = "Field `REQFLAG` writer - Divider status flag. Set when a change is made to the divider value, cleared when the change is complete."]
20pub type ReqflagW<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bits 0:7 - Clock Divider Value Selection. . . 0: Divide by 1. ... 255: Divide by 256."]
23    #[inline(always)]
24    pub fn div(&self) -> DivR {
25        DivR::new((self.bits & 0xff) as u8)
26    }
27    #[doc = "Bit 29 - Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count."]
28    #[inline(always)]
29    pub fn reset(&self) -> ResetR {
30        ResetR::new(((self.bits >> 29) & 1) != 0)
31    }
32    #[doc = "Bit 30 - Halts the divider counter. The intent is to allow the divider's clock source to be changed without the risk of a glitch at the output."]
33    #[inline(always)]
34    pub fn halt(&self) -> HaltR {
35        HaltR::new(((self.bits >> 30) & 1) != 0)
36    }
37    #[doc = "Bit 31 - Divider status flag. Set when a change is made to the divider value, cleared when the change is complete."]
38    #[inline(always)]
39    pub fn reqflag(&self) -> ReqflagR {
40        ReqflagR::new(((self.bits >> 31) & 1) != 0)
41    }
42}
43#[cfg(feature = "debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("FLEXSPIFCLKDIV")
47            .field("div", &self.div())
48            .field("reset", &self.reset())
49            .field("halt", &self.halt())
50            .field("reqflag", &self.reqflag())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:7 - Clock Divider Value Selection. . . 0: Divide by 1. ... 255: Divide by 256."]
56    #[inline(always)]
57    pub fn div(&mut self) -> DivW<FlexspifclkdivSpec> {
58        DivW::new(self, 0)
59    }
60    #[doc = "Bit 29 - Resets the divider counter. Can be used to make sure a new divider value is used right away rather than completing the previous count."]
61    #[inline(always)]
62    pub fn reset(&mut self) -> ResetW<FlexspifclkdivSpec> {
63        ResetW::new(self, 29)
64    }
65    #[doc = "Bit 30 - Halts the divider counter. The intent is to allow the divider's clock source to be changed without the risk of a glitch at the output."]
66    #[inline(always)]
67    pub fn halt(&mut self) -> HaltW<FlexspifclkdivSpec> {
68        HaltW::new(self, 30)
69    }
70    #[doc = "Bit 31 - Divider status flag. Set when a change is made to the divider value, cleared when the change is complete."]
71    #[inline(always)]
72    pub fn reqflag(&mut self) -> ReqflagW<FlexspifclkdivSpec> {
73        ReqflagW::new(self, 31)
74    }
75}
76#[doc = "FlexSPI FCLK divider\n\nYou can [`read`](crate::Reg::read) this register and get [`flexspifclkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flexspifclkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct FlexspifclkdivSpec;
78impl crate::RegisterSpec for FlexspifclkdivSpec {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`flexspifclkdiv::R`](R) reader structure"]
82impl crate::Readable for FlexspifclkdivSpec {}
83#[doc = "`write(|w| ..)` method takes [`flexspifclkdiv::W`](W) writer structure"]
84impl crate::Writable for FlexspifclkdivSpec {
85    type Safety = crate::Unsafe;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets FLEXSPIFCLKDIV to value 0x4000_0000"]
90impl crate::Resettable for FlexspifclkdivSpec {
91    const RESET_VALUE: u32 = 0x4000_0000;
92}
mimxrt685s_pac/clkctl0/flexspifclkdiv.rs

mimxrt685s_pac/clkctl0/
flexspifclkdiv.rs
