1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - Master Configuration Register"]
5 pub mconfig: MCONFIG,
6 #[doc = "0x04 - Slave Configuration Register"]
7 pub sconfig: SCONFIG,
8 #[doc = "0x08 - Slave Status Register"]
9 pub sstatus: SSTATUS,
10 #[doc = "0x0c - Slave Control Register"]
11 pub sctrl: SCTRL,
12 #[doc = "0x10 - Slave Interrupt Set Register"]
13 pub sintset: SINTSET,
14 #[doc = "0x14 - Slave Interrupt Clear Register"]
15 pub sintclr: SINTCLR,
16 #[doc = "0x18 - Slave Interrupt Mask Register"]
17 pub sintmasked: SINTMASKED,
18 #[doc = "0x1c - Slave Errors and Warnings Register"]
19 pub serrwarn: SERRWARN,
20 #[doc = "0x20 - Slave DMA Control Register"]
21 pub sdmactrl: SDMACTRL,
22 _reserved9: [u8; 0x08],
23 #[doc = "0x2c - Slave Data Control Register"]
24 pub sdatactrl: SDATACTRL,
25 #[doc = "0x30 - Slave Write Data Byte Register"]
26 pub swdatab: SWDATAB,
27 #[doc = "0x34 - Slave Write Data Byte End"]
28 pub swdatabe: SWDATABE,
29 #[doc = "0x38 - Slave Write Data Half-word Register"]
30 pub swdatah: SWDATAH,
31 #[doc = "0x3c - Slave Write Data Half-word End Register"]
32 pub swdatahe: SWDATAHE,
33 #[doc = "0x40 - Slave Read Data Byte Register"]
34 pub srdatab: SRDATAB,
35 _reserved15: [u8; 0x04],
36 #[doc = "0x48 - Slave Read Data Half-word Register"]
37 pub srdatah: SRDATAH,
38 _reserved16: [u8; 0x14],
39 #[doc = "0x60 - Slave Capabilities Register"]
40 pub scapabilities: SCAPABILITIES,
41 #[doc = "0x64 - Slave Dynamic Address Register"]
42 pub sdynaddr: SDYNADDR,
43 #[doc = "0x68 - Slave Maximum Limits Register"]
44 pub smaxlimits: SMAXLIMITS,
45 #[doc = "0x6c - Slave ID Part Number Register"]
46 pub sidpartno: SIDPARTNO,
47 #[doc = "0x70 - Slave ID Extension Register"]
48 pub sidext: SIDEXT,
49 #[doc = "0x74 - Slave Vendor ID Register"]
50 pub svendorid: SVENDORID,
51 #[doc = "0x78 - Slave Time Control Clock Register"]
52 pub stcclock: STCCLOCK,
53 #[doc = "0x7c - Slave Message-Mapped Address Register"]
54 pub smsgmapaddr: SMSGMAPADDR,
55 _reserved24: [u8; 0x04],
56 #[doc = "0x84 - Master Main Control Register"]
57 pub mctrl: MCTRL,
58 #[doc = "0x88 - Master Status Register"]
59 pub mstatus: MSTATUS,
60 #[doc = "0x8c - Master In-band Interrupt Registry and Rules Register"]
61 pub mibirules: MIBIRULES,
62 #[doc = "0x90 - Master Interrupt Set Register"]
63 pub mintset: MINTSET,
64 #[doc = "0x94 - Master Interrupt Clear Register"]
65 pub mintclr: MINTCLR,
66 #[doc = "0x98 - Master Interrupt Mask Register"]
67 pub mintmasked: MINTMASKED,
68 #[doc = "0x9c - Master Errors and Warnings Register"]
69 pub merrwarn: MERRWARN,
70 #[doc = "0xa0 - Master DMA Control Register"]
71 pub mdmactrl: MDMACTRL,
72 _reserved32: [u8; 0x08],
73 #[doc = "0xac - Master Data Control Register"]
74 pub mdatactrl: MDATACTRL,
75 #[doc = "0xb0 - Master Write Data Byte Register"]
76 pub mwdatab: MWDATAB,
77 #[doc = "0xb4 - Master Write Data Byte End Register"]
78 pub mwdatabe: MWDATABE,
79 #[doc = "0xb8 - Master Write Data Half-word Register"]
80 pub mwdatah: MWDATAH,
81 #[doc = "0xbc - Master Write Data Byte End Register"]
82 pub mwdatahe: MWDATAHE,
83 #[doc = "0xc0 - Master Read Data Byte Register"]
84 pub mrdatab: MRDATAB,
85 _reserved38: [u8; 0x04],
86 #[doc = "0xc8 - Master Read Data Half-word Register"]
87 pub mrdatah: MRDATAH,
88 #[doc = "0xcc - Write Byte Data 1 (to bus)"]
89 pub mwdatab1: MWDATAB1,
90 _reserved_40_mwmsg_sdr_mwmsg_sdr: [u8; 0x04],
91 #[doc = "0xd4 - Master Read Message in SDR mode"]
92 pub mrmsg_sdr: MRMSG_SDR,
93 _reserved_42_mwmsg_ddr_mwmsg_ddr: [u8; 0x04],
94 #[doc = "0xdc - Master Read Message in DDR mode"]
95 pub mrmsg_ddr: MRMSG_DDR,
96 _reserved44: [u8; 0x04],
97 #[doc = "0xe4 - Master Dynamic Address Register"]
98 pub mdynaddr: MDYNADDR,
99 _reserved45: [u8; 0x0f14],
100 #[doc = "0xffc - Slave Module ID"]
101 pub sid: SID,
102}
103impl RegisterBlock {
104 #[doc = "0xd0 - Master Write Message Data in SDR mode"]
105 #[inline(always)]
106 pub const fn mwmsg_sdr_mwmsg_sdr_data(&self) -> &MWMSG_SDR_MWMSG_SDR_DATA {
107 unsafe { &*(self as *const Self).cast::<u8>().add(208usize).cast() }
108 }
109 #[doc = "0xd0 - Master Write Message in SDR mode"]
110 #[inline(always)]
111 pub const fn mwmsg_sdr_mwmsg_sdr_control(&self) -> &MWMSG_SDR_MWMSG_SDR_CONTROL {
112 unsafe { &*(self as *const Self).cast::<u8>().add(208usize).cast() }
113 }
114 #[doc = "0xd8 - Master Write Message Data in DDR mode"]
115 #[inline(always)]
116 pub const fn mwmsg_ddr_mwmsg_ddr_data(&self) -> &MWMSG_DDR_MWMSG_DDR_DATA {
117 unsafe { &*(self as *const Self).cast::<u8>().add(216usize).cast() }
118 }
119 #[doc = "0xd8 - Master Write Message in DDR mode"]
120 #[inline(always)]
121 pub const fn mwmsg_ddr_mwmsg_ddr_control(&self) -> &MWMSG_DDR_MWMSG_DDR_CONTROL {
122 unsafe { &*(self as *const Self).cast::<u8>().add(216usize).cast() }
123 }
124}
125#[doc = "MCONFIG (rw) register accessor: an alias for `Reg<MCONFIG_SPEC>`"]
126pub type MCONFIG = crate::Reg<mconfig::MCONFIG_SPEC>;
127#[doc = "Master Configuration Register"]
128pub mod mconfig;
129#[doc = "SCONFIG (rw) register accessor: an alias for `Reg<SCONFIG_SPEC>`"]
130pub type SCONFIG = crate::Reg<sconfig::SCONFIG_SPEC>;
131#[doc = "Slave Configuration Register"]
132pub mod sconfig;
133#[doc = "SSTATUS (rw) register accessor: an alias for `Reg<SSTATUS_SPEC>`"]
134pub type SSTATUS = crate::Reg<sstatus::SSTATUS_SPEC>;
135#[doc = "Slave Status Register"]
136pub mod sstatus;
137#[doc = "SCTRL (rw) register accessor: an alias for `Reg<SCTRL_SPEC>`"]
138pub type SCTRL = crate::Reg<sctrl::SCTRL_SPEC>;
139#[doc = "Slave Control Register"]
140pub mod sctrl;
141#[doc = "SINTSET (rw) register accessor: an alias for `Reg<SINTSET_SPEC>`"]
142pub type SINTSET = crate::Reg<sintset::SINTSET_SPEC>;
143#[doc = "Slave Interrupt Set Register"]
144pub mod sintset;
145#[doc = "SINTCLR (rw) register accessor: an alias for `Reg<SINTCLR_SPEC>`"]
146pub type SINTCLR = crate::Reg<sintclr::SINTCLR_SPEC>;
147#[doc = "Slave Interrupt Clear Register"]
148pub mod sintclr;
149#[doc = "SINTMASKED (r) register accessor: an alias for `Reg<SINTMASKED_SPEC>`"]
150pub type SINTMASKED = crate::Reg<sintmasked::SINTMASKED_SPEC>;
151#[doc = "Slave Interrupt Mask Register"]
152pub mod sintmasked;
153#[doc = "SERRWARN (rw) register accessor: an alias for `Reg<SERRWARN_SPEC>`"]
154pub type SERRWARN = crate::Reg<serrwarn::SERRWARN_SPEC>;
155#[doc = "Slave Errors and Warnings Register"]
156pub mod serrwarn;
157#[doc = "SDMACTRL (rw) register accessor: an alias for `Reg<SDMACTRL_SPEC>`"]
158pub type SDMACTRL = crate::Reg<sdmactrl::SDMACTRL_SPEC>;
159#[doc = "Slave DMA Control Register"]
160pub mod sdmactrl;
161#[doc = "SDATACTRL (rw) register accessor: an alias for `Reg<SDATACTRL_SPEC>`"]
162pub type SDATACTRL = crate::Reg<sdatactrl::SDATACTRL_SPEC>;
163#[doc = "Slave Data Control Register"]
164pub mod sdatactrl;
165#[doc = "SWDATAB (w) register accessor: an alias for `Reg<SWDATAB_SPEC>`"]
166pub type SWDATAB = crate::Reg<swdatab::SWDATAB_SPEC>;
167#[doc = "Slave Write Data Byte Register"]
168pub mod swdatab;
169#[doc = "SWDATABE (w) register accessor: an alias for `Reg<SWDATABE_SPEC>`"]
170pub type SWDATABE = crate::Reg<swdatabe::SWDATABE_SPEC>;
171#[doc = "Slave Write Data Byte End"]
172pub mod swdatabe;
173#[doc = "SWDATAH (w) register accessor: an alias for `Reg<SWDATAH_SPEC>`"]
174pub type SWDATAH = crate::Reg<swdatah::SWDATAH_SPEC>;
175#[doc = "Slave Write Data Half-word Register"]
176pub mod swdatah;
177#[doc = "SWDATAHE (w) register accessor: an alias for `Reg<SWDATAHE_SPEC>`"]
178pub type SWDATAHE = crate::Reg<swdatahe::SWDATAHE_SPEC>;
179#[doc = "Slave Write Data Half-word End Register"]
180pub mod swdatahe;
181#[doc = "SRDATAB (r) register accessor: an alias for `Reg<SRDATAB_SPEC>`"]
182pub type SRDATAB = crate::Reg<srdatab::SRDATAB_SPEC>;
183#[doc = "Slave Read Data Byte Register"]
184pub mod srdatab;
185#[doc = "SRDATAH (r) register accessor: an alias for `Reg<SRDATAH_SPEC>`"]
186pub type SRDATAH = crate::Reg<srdatah::SRDATAH_SPEC>;
187#[doc = "Slave Read Data Half-word Register"]
188pub mod srdatah;
189#[doc = "SCAPABILITIES (r) register accessor: an alias for `Reg<SCAPABILITIES_SPEC>`"]
190pub type SCAPABILITIES = crate::Reg<scapabilities::SCAPABILITIES_SPEC>;
191#[doc = "Slave Capabilities Register"]
192pub mod scapabilities;
193#[doc = "SDYNADDR (rw) register accessor: an alias for `Reg<SDYNADDR_SPEC>`"]
194pub type SDYNADDR = crate::Reg<sdynaddr::SDYNADDR_SPEC>;
195#[doc = "Slave Dynamic Address Register"]
196pub mod sdynaddr;
197#[doc = "SMAXLIMITS (rw) register accessor: an alias for `Reg<SMAXLIMITS_SPEC>`"]
198pub type SMAXLIMITS = crate::Reg<smaxlimits::SMAXLIMITS_SPEC>;
199#[doc = "Slave Maximum Limits Register"]
200pub mod smaxlimits;
201#[doc = "SIDPARTNO (rw) register accessor: an alias for `Reg<SIDPARTNO_SPEC>`"]
202pub type SIDPARTNO = crate::Reg<sidpartno::SIDPARTNO_SPEC>;
203#[doc = "Slave ID Part Number Register"]
204pub mod sidpartno;
205#[doc = "SIDEXT (rw) register accessor: an alias for `Reg<SIDEXT_SPEC>`"]
206pub type SIDEXT = crate::Reg<sidext::SIDEXT_SPEC>;
207#[doc = "Slave ID Extension Register"]
208pub mod sidext;
209#[doc = "SVENDORID (rw) register accessor: an alias for `Reg<SVENDORID_SPEC>`"]
210pub type SVENDORID = crate::Reg<svendorid::SVENDORID_SPEC>;
211#[doc = "Slave Vendor ID Register"]
212pub mod svendorid;
213#[doc = "STCCLOCK (rw) register accessor: an alias for `Reg<STCCLOCK_SPEC>`"]
214pub type STCCLOCK = crate::Reg<stcclock::STCCLOCK_SPEC>;
215#[doc = "Slave Time Control Clock Register"]
216pub mod stcclock;
217#[doc = "SMSGMAPADDR (r) register accessor: an alias for `Reg<SMSGMAPADDR_SPEC>`"]
218pub type SMSGMAPADDR = crate::Reg<smsgmapaddr::SMSGMAPADDR_SPEC>;
219#[doc = "Slave Message-Mapped Address Register"]
220pub mod smsgmapaddr;
221#[doc = "MCTRL (rw) register accessor: an alias for `Reg<MCTRL_SPEC>`"]
222pub type MCTRL = crate::Reg<mctrl::MCTRL_SPEC>;
223#[doc = "Master Main Control Register"]
224pub mod mctrl;
225#[doc = "MSTATUS (rw) register accessor: an alias for `Reg<MSTATUS_SPEC>`"]
226pub type MSTATUS = crate::Reg<mstatus::MSTATUS_SPEC>;
227#[doc = "Master Status Register"]
228pub mod mstatus;
229#[doc = "MIBIRULES (rw) register accessor: an alias for `Reg<MIBIRULES_SPEC>`"]
230pub type MIBIRULES = crate::Reg<mibirules::MIBIRULES_SPEC>;
231#[doc = "Master In-band Interrupt Registry and Rules Register"]
232pub mod mibirules;
233#[doc = "MINTSET (rw) register accessor: an alias for `Reg<MINTSET_SPEC>`"]
234pub type MINTSET = crate::Reg<mintset::MINTSET_SPEC>;
235#[doc = "Master Interrupt Set Register"]
236pub mod mintset;
237#[doc = "MINTCLR (w) register accessor: an alias for `Reg<MINTCLR_SPEC>`"]
238pub type MINTCLR = crate::Reg<mintclr::MINTCLR_SPEC>;
239#[doc = "Master Interrupt Clear Register"]
240pub mod mintclr;
241#[doc = "MINTMASKED (r) register accessor: an alias for `Reg<MINTMASKED_SPEC>`"]
242pub type MINTMASKED = crate::Reg<mintmasked::MINTMASKED_SPEC>;
243#[doc = "Master Interrupt Mask Register"]
244pub mod mintmasked;
245#[doc = "MERRWARN (rw) register accessor: an alias for `Reg<MERRWARN_SPEC>`"]
246pub type MERRWARN = crate::Reg<merrwarn::MERRWARN_SPEC>;
247#[doc = "Master Errors and Warnings Register"]
248pub mod merrwarn;
249#[doc = "MDMACTRL (rw) register accessor: an alias for `Reg<MDMACTRL_SPEC>`"]
250pub type MDMACTRL = crate::Reg<mdmactrl::MDMACTRL_SPEC>;
251#[doc = "Master DMA Control Register"]
252pub mod mdmactrl;
253#[doc = "MDATACTRL (rw) register accessor: an alias for `Reg<MDATACTRL_SPEC>`"]
254pub type MDATACTRL = crate::Reg<mdatactrl::MDATACTRL_SPEC>;
255#[doc = "Master Data Control Register"]
256pub mod mdatactrl;
257#[doc = "MWDATAB (w) register accessor: an alias for `Reg<MWDATAB_SPEC>`"]
258pub type MWDATAB = crate::Reg<mwdatab::MWDATAB_SPEC>;
259#[doc = "Master Write Data Byte Register"]
260pub mod mwdatab;
261#[doc = "MWDATABE (w) register accessor: an alias for `Reg<MWDATABE_SPEC>`"]
262pub type MWDATABE = crate::Reg<mwdatabe::MWDATABE_SPEC>;
263#[doc = "Master Write Data Byte End Register"]
264pub mod mwdatabe;
265#[doc = "MWDATAH (w) register accessor: an alias for `Reg<MWDATAH_SPEC>`"]
266pub type MWDATAH = crate::Reg<mwdatah::MWDATAH_SPEC>;
267#[doc = "Master Write Data Half-word Register"]
268pub mod mwdatah;
269#[doc = "MWDATAHE (w) register accessor: an alias for `Reg<MWDATAHE_SPEC>`"]
270pub type MWDATAHE = crate::Reg<mwdatahe::MWDATAHE_SPEC>;
271#[doc = "Master Write Data Byte End Register"]
272pub mod mwdatahe;
273#[doc = "MRDATAB (r) register accessor: an alias for `Reg<MRDATAB_SPEC>`"]
274pub type MRDATAB = crate::Reg<mrdatab::MRDATAB_SPEC>;
275#[doc = "Master Read Data Byte Register"]
276pub mod mrdatab;
277#[doc = "MRDATAH (r) register accessor: an alias for `Reg<MRDATAH_SPEC>`"]
278pub type MRDATAH = crate::Reg<mrdatah::MRDATAH_SPEC>;
279#[doc = "Master Read Data Half-word Register"]
280pub mod mrdatah;
281#[doc = "MWDATAB1 (w) register accessor: an alias for `Reg<MWDATAB1_SPEC>`"]
282pub type MWDATAB1 = crate::Reg<mwdatab1::MWDATAB1_SPEC>;
283#[doc = "Write Byte Data 1 (to bus)"]
284pub mod mwdatab1;
285#[doc = "MWMSG_SDR_MWMSG_SDR_CONTROL (w) register accessor: an alias for `Reg<MWMSG_SDR_MWMSG_SDR_CONTROL_SPEC>`"]
286pub type MWMSG_SDR_MWMSG_SDR_CONTROL =
287 crate::Reg<mwmsg_sdr_mwmsg_sdr_control::MWMSG_SDR_MWMSG_SDR_CONTROL_SPEC>;
288#[doc = "Master Write Message in SDR mode"]
289pub mod mwmsg_sdr_mwmsg_sdr_control;
290#[doc = "MWMSG_SDR_MWMSG_SDR_DATA (w) register accessor: an alias for `Reg<MWMSG_SDR_MWMSG_SDR_DATA_SPEC>`"]
291pub type MWMSG_SDR_MWMSG_SDR_DATA =
292 crate::Reg<mwmsg_sdr_mwmsg_sdr_data::MWMSG_SDR_MWMSG_SDR_DATA_SPEC>;
293#[doc = "Master Write Message Data in SDR mode"]
294pub mod mwmsg_sdr_mwmsg_sdr_data;
295#[doc = "MRMSG_SDR (r) register accessor: an alias for `Reg<MRMSG_SDR_SPEC>`"]
296pub type MRMSG_SDR = crate::Reg<mrmsg_sdr::MRMSG_SDR_SPEC>;
297#[doc = "Master Read Message in SDR mode"]
298pub mod mrmsg_sdr;
299#[doc = "MWMSG_DDR_MWMSG_DDR_CONTROL (w) register accessor: an alias for `Reg<MWMSG_DDR_MWMSG_DDR_CONTROL_SPEC>`"]
300pub type MWMSG_DDR_MWMSG_DDR_CONTROL =
301 crate::Reg<mwmsg_ddr_mwmsg_ddr_control::MWMSG_DDR_MWMSG_DDR_CONTROL_SPEC>;
302#[doc = "Master Write Message in DDR mode"]
303pub mod mwmsg_ddr_mwmsg_ddr_control;
304#[doc = "MWMSG_DDR_MWMSG_DDR_DATA (w) register accessor: an alias for `Reg<MWMSG_DDR_MWMSG_DDR_DATA_SPEC>`"]
305pub type MWMSG_DDR_MWMSG_DDR_DATA =
306 crate::Reg<mwmsg_ddr_mwmsg_ddr_data::MWMSG_DDR_MWMSG_DDR_DATA_SPEC>;
307#[doc = "Master Write Message Data in DDR mode"]
308pub mod mwmsg_ddr_mwmsg_ddr_data;
309#[doc = "MRMSG_DDR (rw) register accessor: an alias for `Reg<MRMSG_DDR_SPEC>`"]
310pub type MRMSG_DDR = crate::Reg<mrmsg_ddr::MRMSG_DDR_SPEC>;
311#[doc = "Master Read Message in DDR mode"]
312pub mod mrmsg_ddr;
313#[doc = "MDYNADDR (rw) register accessor: an alias for `Reg<MDYNADDR_SPEC>`"]
314pub type MDYNADDR = crate::Reg<mdynaddr::MDYNADDR_SPEC>;
315#[doc = "Master Dynamic Address Register"]
316pub mod mdynaddr;
317#[doc = "SID (r) register accessor: an alias for `Reg<SID_SPEC>`"]
318pub type SID = crate::Reg<sid::SID_SPEC>;
319#[doc = "Slave Module ID"]
320pub mod sid;