mimxrt595s/clkctl0/
lowfreqclkdiv.rs

1#[doc = "Register `LOWFREQCLKDIV` reader"]
2pub struct R(crate::R<LOWFREQCLKDIV_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<LOWFREQCLKDIV_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<LOWFREQCLKDIV_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<LOWFREQCLKDIV_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `LOWFREQCLKDIV` writer"]
17pub struct W(crate::W<LOWFREQCLKDIV_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<LOWFREQCLKDIV_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<LOWFREQCLKDIV_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<LOWFREQCLKDIV_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `DIV` reader - Low Frequency Clock Divider Value"]
38pub type DIV_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `DIV` writer - Low Frequency Clock Divider Value"]
40pub type DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LOWFREQCLKDIV_SPEC, u8, u8, 8, O>;
41#[doc = "Field `RESET` reader - Reset the Divider Counter"]
42pub type RESET_R = crate::BitReader<RESET_A>;
43#[doc = "Reset the Divider Counter\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45pub enum RESET_A {
46    #[doc = "0: No effect"]
47    DIVIDER_COUNTER_NOT_RESET = 0,
48    #[doc = "1: Reset the Divider Counter"]
49    DIVIDER_COUNTER_RESET = 1,
50}
51impl From<RESET_A> for bool {
52    #[inline(always)]
53    fn from(variant: RESET_A) -> Self {
54        variant as u8 != 0
55    }
56}
57impl RESET_R {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> RESET_A {
61        match self.bits {
62            false => RESET_A::DIVIDER_COUNTER_NOT_RESET,
63            true => RESET_A::DIVIDER_COUNTER_RESET,
64        }
65    }
66    #[doc = "Checks if the value of the field is `DIVIDER_COUNTER_NOT_RESET`"]
67    #[inline(always)]
68    pub fn is_divider_counter_not_reset(&self) -> bool {
69        *self == RESET_A::DIVIDER_COUNTER_NOT_RESET
70    }
71    #[doc = "Checks if the value of the field is `DIVIDER_COUNTER_RESET`"]
72    #[inline(always)]
73    pub fn is_divider_counter_reset(&self) -> bool {
74        *self == RESET_A::DIVIDER_COUNTER_RESET
75    }
76}
77#[doc = "Field `RESET` writer - Reset the Divider Counter"]
78pub type RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, LOWFREQCLKDIV_SPEC, RESET_A, O>;
79impl<'a, const O: u8> RESET_W<'a, O> {
80    #[doc = "No effect"]
81    #[inline(always)]
82    pub fn divider_counter_not_reset(self) -> &'a mut W {
83        self.variant(RESET_A::DIVIDER_COUNTER_NOT_RESET)
84    }
85    #[doc = "Reset the Divider Counter"]
86    #[inline(always)]
87    pub fn divider_counter_reset(self) -> &'a mut W {
88        self.variant(RESET_A::DIVIDER_COUNTER_RESET)
89    }
90}
91#[doc = "Field `HALT` reader - Halt the Divider Counter"]
92pub type HALT_R = crate::BitReader<HALT_A>;
93#[doc = "Halt the Divider Counter\n\nValue on reset: 0"]
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum HALT_A {
96    #[doc = "0: No effect"]
97    DIVIDER_COUNTER_NOT_HALT = 0,
98    #[doc = "1: Halt (stop) the Divider Counter"]
99    DIVIDER_COUNTER_HALT = 1,
100}
101impl From<HALT_A> for bool {
102    #[inline(always)]
103    fn from(variant: HALT_A) -> Self {
104        variant as u8 != 0
105    }
106}
107impl HALT_R {
108    #[doc = "Get enumerated values variant"]
109    #[inline(always)]
110    pub fn variant(&self) -> HALT_A {
111        match self.bits {
112            false => HALT_A::DIVIDER_COUNTER_NOT_HALT,
113            true => HALT_A::DIVIDER_COUNTER_HALT,
114        }
115    }
116    #[doc = "Checks if the value of the field is `DIVIDER_COUNTER_NOT_HALT`"]
117    #[inline(always)]
118    pub fn is_divider_counter_not_halt(&self) -> bool {
119        *self == HALT_A::DIVIDER_COUNTER_NOT_HALT
120    }
121    #[doc = "Checks if the value of the field is `DIVIDER_COUNTER_HALT`"]
122    #[inline(always)]
123    pub fn is_divider_counter_halt(&self) -> bool {
124        *self == HALT_A::DIVIDER_COUNTER_HALT
125    }
126}
127#[doc = "Field `HALT` writer - Halt the Divider Counter"]
128pub type HALT_W<'a, const O: u8> = crate::BitWriter<'a, u32, LOWFREQCLKDIV_SPEC, HALT_A, O>;
129impl<'a, const O: u8> HALT_W<'a, O> {
130    #[doc = "No effect"]
131    #[inline(always)]
132    pub fn divider_counter_not_halt(self) -> &'a mut W {
133        self.variant(HALT_A::DIVIDER_COUNTER_NOT_HALT)
134    }
135    #[doc = "Halt (stop) the Divider Counter"]
136    #[inline(always)]
137    pub fn divider_counter_halt(self) -> &'a mut W {
138        self.variant(HALT_A::DIVIDER_COUNTER_HALT)
139    }
140}
141#[doc = "Field `REQFLAG` reader - Divider Status Flag"]
142pub type REQFLAG_R = crate::BitReader<REQFLAG_A>;
143#[doc = "Divider Status Flag\n\nValue on reset: 0"]
144#[derive(Clone, Copy, Debug, PartialEq, Eq)]
145pub enum REQFLAG_A {
146    #[doc = "0: The Divider change has finished"]
147    REQFLAG_CHANGE_FINISHED = 0,
148    #[doc = "1: The Divider value has changed"]
149    REQFLAG_CHANGED = 1,
150}
151impl From<REQFLAG_A> for bool {
152    #[inline(always)]
153    fn from(variant: REQFLAG_A) -> Self {
154        variant as u8 != 0
155    }
156}
157impl REQFLAG_R {
158    #[doc = "Get enumerated values variant"]
159    #[inline(always)]
160    pub fn variant(&self) -> REQFLAG_A {
161        match self.bits {
162            false => REQFLAG_A::REQFLAG_CHANGE_FINISHED,
163            true => REQFLAG_A::REQFLAG_CHANGED,
164        }
165    }
166    #[doc = "Checks if the value of the field is `REQFLAG_CHANGE_FINISHED`"]
167    #[inline(always)]
168    pub fn is_reqflag_change_finished(&self) -> bool {
169        *self == REQFLAG_A::REQFLAG_CHANGE_FINISHED
170    }
171    #[doc = "Checks if the value of the field is `REQFLAG_CHANGED`"]
172    #[inline(always)]
173    pub fn is_reqflag_changed(&self) -> bool {
174        *self == REQFLAG_A::REQFLAG_CHANGED
175    }
176}
177#[doc = "Field `REQFLAG` writer - Divider Status Flag"]
178pub type REQFLAG_W<'a, const O: u8> = crate::BitWriter<'a, u32, LOWFREQCLKDIV_SPEC, REQFLAG_A, O>;
179impl<'a, const O: u8> REQFLAG_W<'a, O> {
180    #[doc = "The Divider change has finished"]
181    #[inline(always)]
182    pub fn reqflag_change_finished(self) -> &'a mut W {
183        self.variant(REQFLAG_A::REQFLAG_CHANGE_FINISHED)
184    }
185    #[doc = "The Divider value has changed"]
186    #[inline(always)]
187    pub fn reqflag_changed(self) -> &'a mut W {
188        self.variant(REQFLAG_A::REQFLAG_CHANGED)
189    }
190}
191impl R {
192    #[doc = "Bits 0:7 - Low Frequency Clock Divider Value"]
193    #[inline(always)]
194    pub fn div(&self) -> DIV_R {
195        DIV_R::new((self.bits & 0xff) as u8)
196    }
197    #[doc = "Bit 29 - Reset the Divider Counter"]
198    #[inline(always)]
199    pub fn reset(&self) -> RESET_R {
200        RESET_R::new(((self.bits >> 29) & 1) != 0)
201    }
202    #[doc = "Bit 30 - Halt the Divider Counter"]
203    #[inline(always)]
204    pub fn halt(&self) -> HALT_R {
205        HALT_R::new(((self.bits >> 30) & 1) != 0)
206    }
207    #[doc = "Bit 31 - Divider Status Flag"]
208    #[inline(always)]
209    pub fn reqflag(&self) -> REQFLAG_R {
210        REQFLAG_R::new(((self.bits >> 31) & 1) != 0)
211    }
212}
213impl W {
214    #[doc = "Bits 0:7 - Low Frequency Clock Divider Value"]
215    #[inline(always)]
216    #[must_use]
217    pub fn div(&mut self) -> DIV_W<0> {
218        DIV_W::new(self)
219    }
220    #[doc = "Bit 29 - Reset the Divider Counter"]
221    #[inline(always)]
222    #[must_use]
223    pub fn reset(&mut self) -> RESET_W<29> {
224        RESET_W::new(self)
225    }
226    #[doc = "Bit 30 - Halt the Divider Counter"]
227    #[inline(always)]
228    #[must_use]
229    pub fn halt(&mut self) -> HALT_W<30> {
230        HALT_W::new(self)
231    }
232    #[doc = "Bit 31 - Divider Status Flag"]
233    #[inline(always)]
234    #[must_use]
235    pub fn reqflag(&mut self) -> REQFLAG_W<31> {
236        REQFLAG_W::new(self)
237    }
238    #[doc = "Writes raw bits to the register."]
239    #[inline(always)]
240    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
241        self.0.bits(bits);
242        self
243    }
244}
245#[doc = "Low Frequency Clock Divider\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lowfreqclkdiv](index.html) module"]
246pub struct LOWFREQCLKDIV_SPEC;
247impl crate::RegisterSpec for LOWFREQCLKDIV_SPEC {
248    type Ux = u32;
249}
250#[doc = "`read()` method returns [lowfreqclkdiv::R](R) reader structure"]
251impl crate::Readable for LOWFREQCLKDIV_SPEC {
252    type Reader = R;
253}
254#[doc = "`write(|w| ..)` method takes [lowfreqclkdiv::W](W) writer structure"]
255impl crate::Writable for LOWFREQCLKDIV_SPEC {
256    type Writer = W;
257    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
258    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
259}
260#[doc = "`reset()` method sets LOWFREQCLKDIV to value 0"]
261impl crate::Resettable for LOWFREQCLKDIV_SPEC {
262    const RESET_VALUE: Self::Ux = 0;
263}
mimxrt595s/clkctl0/lowfreqclkdiv.rs

mimxrt595s/clkctl0/
lowfreqclkdiv.rs
